PMULHW instruction (MMX, SSE2)

PMULHW multiplies signed words and keeps the high 16 bits of each 32-bit product: 8 results in an XMM register, 4 in an MMX register. PMULLW keeps the low halves of the same products, and the pair together gives the full products. The high half is the product shifted right by 16 with the sign kept, so it rounds toward minus infinity. On Zen 5, the recorded pmulhw xmm8, xmm15 gave 4000h for 8000h times 8000h, 3FFFh for 7FFFh times 7FFFh, 0000h for 7FFFh times 1, but FFFFh for 8000h times 1 and for 7FFFh times FFFFh: a small negative product has a high half of -1, not 0.

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

High halves. a[i] = ((int32_t)b[i] * c[i]) >> 16 over int16_t is PMULHW alone, as is _mm_mulhi_epi16.
Division by a constant. b[i] / 7 multiplies by a constant whose high half, shifted right by 1 with PSRAW, is the quotient rounded down; adding 1 to negative elements (GCC subtracts the sign mask, Clang adds the sign bit from PSRLW by 15) makes it round toward zero as C requires. Unsigned words use PMULHUW the same way.
Widening products. For (int32_t)b[i] * c[i], GCC computes both halves with PMULLW and PMULHW and interleaves them into doublewords with PUNPCKLWD and PUNPCKHWD. Clang puts each word of one operand next to a zero and uses PMADDWD.
Q15 products. ((int32_t)b[i] * c[i]) >> 15 needs bit 15 of the product too, so neither compiler uses PMULHW alone: GCC builds the full products as above and shifts them with PSRAD, Clang uses PMADDWD. SSSE3’s PMULHRSW gives these bits with rounding.

Intel’s optimization manual describes the high and low multiplies together (Section 6.6.8). AMD’s latency spreadsheet for Zen 5 gives the XMM form three cycles, two per cycle, as for the other word multiplies. The MMX form came with MMX and the XMM form with SSE2; the legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes. VPMULHW is the VEX and EVEX form.

Forms

Every encoding of PMULHW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMULHW mm, m64` PMULHW_MMXq_MEMq	`NP 0F E5 /r`	MMX
`PMULHW mm, mm` PMULHW_MMXq_MMXq	`NP 0F E5 /r`	MMX
`PMULHW xmm, m128` PMULHW_XMMdq_MEMdq	`66 0F E5 /r`	SSE2
`PMULHW xmm, xmm` PMULHW_XMMdq_XMMdq	`66 0F E5 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMULHW mm, mm/m64

for i in range(4):
    mm1.w[i] = mm1.sw[i] * src2.sw[i] >> 16
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMULHW xmm, xmm/m128

for i in range(8):
    sa = xmm1.sw[i]
    sb = src2.sw[i]
    xmm1.w[i] = sa * sb >> 16
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMULHW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMULHW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMULHW mm, m64: mmx-mem
PMULHW mm, mm: none in XED
PMULHW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMULHW mm, mm/m64: may abort a TSX transaction
PMULHW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMULHW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mulhi_epi16` `__m128i _mm_mulhi_epi16(__m128i __a, __m128i __b)`	`PMULHW xmm, xmm` Legacy -msse2
`_mm_mulhi_pi16` `__m64 _mm_mulhi_pi16(__m64 __m1, __m64 __m2)`	`PMULHW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#