PMULLD instruction (SSE4.1)

PMULLD multiplies doublewords element by element and keeps the low 32 bits of each 64-bit product. Those bits are the same whether the inputs are read as signed or as unsigned, so one instruction serves both, and the high halves are simply lost: nothing reports that a product did not fit.

Before SSE4.1

PMULLD came with SSE4.1, which is part of x86-64-v2 but not of the baseline. SSE2 has only PMULUDQ, which multiplies the even-numbered unsigned doublewords (0 and 2) into two full 64-bit products. Compiling for the baseline, GCC 14 and Clang 23 at -O2 vectorize a[i] = b[i] * c[i] over arrays of 1,024 ints with two PMULUDQs, one on the even elements and one on the odd ones moved into even positions, then gather the low halves with PSHUFD and PUNPCKLDQ. With -msse4.1 the loop body becomes MOVDQU, PMULLD and a store. With a count known only at run time, GCC 14 at -O2 keeps this loop and those below scalar, with IMUL or LEA, for either target, while Clang 23 vectorizes them in the same way.

Multiplying by a constant

Compilers weigh PMULLD against shifts and additions. With SSE4.1, GCC 14 at -O2 still compiles a[i] *= 3 to a shift by 1 and a PADDD, and a[i] *= 10 to two shifts and an addition, keeping PMULLD for 12345; for the baseline it builds even 12345 from four shifts and four additions and subtractions. Clang 23 computes x + x + x for 3 but multiplies by 10 with PMULLD. Intel’s optimization guide notes that on Skylake client cores VPMULLD is decoded into two micro-ops, each of which can add a cycle of delay where its result passes to the next instruction (Section 2.7.2).

Other widths

PMULLW and PMULHW keep the low and the high halves of word products, and PMULDQ is the signed counterpart of PMULUDQ. A low 64-bit product per element, VPMULLQ, came only with AVX-512DQ: without it, Clang 23 builds a[i] = b[i] * c[i] on longs from three PMULUDQs per vector, and GCC 14 keeps the loop scalar, with IMUL. VPMULLD is the VEX and EVEX form of PMULLD.

In the optimization guide

What the optimization guide says about PMULLD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Front end: On Silvermont these instructions come from the microcode ROM; Goldmont decodes them directly, except an indirect call through memory.
Vectors and cryptography: pshufb, pmulld, paddq and psubq are slow on Silvermont and much faster from Goldmont on.

Forms

Every encoding of PMULLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMULLD xmm, m128` PMULLD_XMMdq_MEMdq	`66 0F 38 40 /r`	SSE4.1
`PMULLD xmm, xmm` PMULLD_XMMdq_XMMdq	`66 0F 38 40 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: a3×b3, a2×b2, a1×b1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = xmm1.d[i] * src2.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMULLD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMULLD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mullo_epi32` `__m128i _mm_mullo_epi32(__m128i __V1, __m128i __V2)`	`PMULLD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Before SSE4.1#

Multiplying by a constant#

Other widths#