PMULLW instruction (MMX, SSE2)

PMULLW multiplies words and keeps the low 16 bits of each 32-bit product: 8 results in an XMM register, 4 in an MMX register. Those bits are the same whether the words are read as signed or unsigned, so one instruction serves int16_t and uint16_t alike, and a product that does not fit simply wraps. On Zen 5, the recorded pmullw xmm7, [mem] gave 8000h for 8000h times FFFFh (-32768 times -1), 8001h for 7FFFh times FFFFh, 0000h for 8000h times 8000h and 0001h for 7FFFh times 7FFFh. PMULHW and PMULHUW keep the signed and unsigned high halves.

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

Word products. a[i] = b[i] * c[i] over int16_t is one PMULLW per 8 words. By a constant they differ: for 10, GCC shifts and adds with PSLLW and PADDW, Clang multiplies with PMULLW; for 12345 both multiply.
Byte products. There is no byte multiply. For uint8_t, both widen the bytes to words with PUNPCKLBW and PUNPCKHBW, multiply with PMULLW, keep the low byte of each word with a PAND and narrow with PACKUSWB. The bytes need not be zero-extended, as only the low 8 bits of each product count; with -march=x86-64-v2, Clang computes the odd bytes with PMADDUBSW instead.
Full products. For (int32_t)b[i] * c[i] and its unsigned version, GCC computes the low halves with PMULLW and the high ones with PMULHW or PMULHUW and interleaves them with PUNPCKLWD and PUNPCKHWD. Clang does the same for the unsigned version but uses PMADDWD for the signed one, and with -v2 zero-extends to doublewords and multiplies those with PMULLD or PMADDWD.

Intel’s optimization manual describes the low and high word multiplies together (Section 6.6.8). AMD’s latency spreadsheet for Zen 5 gives the XMM form three cycles, two per cycle, as for PMULHW. The MMX form came with MMX and the XMM form with SSE2; the legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes. VPMULLW is the VEX and EVEX form.

Forms

Every encoding of PMULLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMULLW mm, m64` PMULLW_MMXq_MEMq	`NP 0F D5 /r`	MMX
`PMULLW mm, mm` PMULLW_MMXq_MMXq	`NP 0F D5 /r`	MMX
`PMULLW xmm, m128` PMULLW_XMMdq_MEMdq	`66 0F D5 /r`	SSE2
`PMULLW xmm, xmm` PMULLW_XMMdq_XMMdq	`66 0F D5 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: a7×b7, a6×b6, a5×b5, a4×b4, a3×b3, a2×b2, a1×b1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMULLW mm, mm/m64

for i in range(4):
    mm1.w[i] = mm1.w[i] * src2.w[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMULLW xmm, xmm/m128

for i in range(8):
    xmm1.w[i] = xmm1.w[i] * src2.w[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMULLW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMULLW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMULLW mm, mm/m64: mmx-mem
PMULLW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMULLW mm, mm/m64: may abort a TSX transaction
PMULLW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMULLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mullo_epi16` `__m128i _mm_mullo_epi16(__m128i __a, __m128i __b)`	`PMULLW xmm, xmm` Legacy -msse2
`_mm_mullo_pi16` `__m64 _mm_mullo_pi16(__m64 __m1, __m64 __m2)`	`PMULLW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#