PMULUDQ instruction (SSE2)

PMULUDQ multiplies unsigned doublewords into full 64-bit products, but only the even-numbered ones: the low doubleword of each quadword of the destination times the low doubleword of the matching quadword of the source, giving two products in an XMM register and one in an MMX register. The odd doublewords are ignored, so data is moved into the even positions first. It was SSE2’s only doubleword multiply; PMULLD, which keeps the low halves of four products, came with SSE4.1, and PMULDQ, the signed form of PMULUDQ, with it.

Three jobs keep it busy in compiled code, here from GCC 14 and Clang 23 at -O2 for the SSE2 baseline:

Widening products. For w[i] = (uint64_t)u[i] * v[i], both compilers spread the 32-bit inputs over the even positions, GCC with PUNPCKLDQ and PUNPCKHDQ of a register with itself, Clang with PSHUFD, and multiply with PMULUDQ.
Division by a constant. u[i] = v[i] / 7 becomes a multiplication by 24924925h of which only the high 32 bits count. Both compilers compute those with two PMULUDQs, one on the even elements and one on the odd ones shifted down, then subtract, shift and add to finish the quotient. SSE has no instruction that returns the high halves of doubleword products.
Wider multiplications. A low 64-bit product of quadwords is three PMULUDQs and some shifts and additions, as the PMULLD page shows, until AVX-512DQ’s VPMULLQ.

Large-number arithmetic uses it too. Intel’s optimization manual describes modular multiplication for RSA with VPMULUDQ: the numbers are split into digits of 29 bits, so that the 64-bit products and their sums leave headroom and PADDQ can add them without carries between elements (Section 15.16.2). AVX512_IFMA’s VPMADD52LUQ takes the same idea to 52-bit digits.

The MMX form came with SSE2, not with MMX, and multiplies one pair. The legacy SSE2 form needs a memory operand aligned to 16 bytes. The VEX and EVEX forms, VPMULUDQ, also read only the even doublewords, and the EVEX form can broadcast one quadword from memory, of which again only the low half counts.

Forms

Every encoding of PMULUDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMULUDQ mm, m64` PMULUDQ_MMXq_MEMq	`NP 0F F4 /r`	SSE2 + MMX
`PMULUDQ mm, mm` PMULUDQ_MMXq_MMXq	`NP 0F F4 /r`	SSE2 + MMX
`PMULUDQ xmm, m128` PMULUDQ_XMMdq_MEMdq	`66 0F F4 /r`	SSE2
`PMULUDQ xmm, xmm` PMULUDQ_XMMdq_XMMdq	`66 0F F4 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The even doublewords only: doublewords 2 and 0 of the sources make quadwords 1 and 0 of the result, and so on.

Result quadword i comes from doubleword 2i of xmm1 and xmm2. Result quadwords 1 to 0: a2, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMULUDQ mm, mm/m64

i = 0
mm1.q[i] = mm1.d[2 * i] * src2.d[2 * i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMULUDQ xmm, xmm/m128

for i in range(2):
    a = xmm1.d[2 * i]
    b = src2.d[2 * i]
    xmm1.q[i] = a * b
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMULUDQ mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMULUDQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMULUDQ mm, mm/m64: mmx-mem
PMULUDQ xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMULUDQ mm, mm/m64: may abort a TSX transaction
PMULUDQ xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMULUDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mul_epu32` `__m128i _mm_mul_epu32(__m128i __a, __m128i __b)`	`PMULUDQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2MMX` SSE2	SSE2 + MMX `CPUID.01H:EDX[26]` SSE2 `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions