x86-64.net

Instruction

POP

Loads the value on top of the stack into a register, memory or a segment register and moves the stack pointer past it.

Extensions
Forms
8 (8 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of POP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
POP m16/32/64 POP_MEMv8F /0Base instruction set
POP r16/32/64 POP_GPRv_8F8F /0Base instruction set
POP ES not in 64-bit mode POP_ES07Base instruction set
POP SS not in 64-bit mode POP_SS17Base instruction set
POP DS not in 64-bit mode POP_DS1FBase instruction set
POP r16/32/64 POP_GPRv_5858+r
REX2.W0 58+r		Base instruction set
POP FS POP_FS0F A1Base instruction set
POP GS POP_GS0F A9Base instruction set

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.