POP2 instruction (APX)

POP2 a, b behaves like POP a followed by POP b, with a in the EVEX V field and b in ModRM.rm, so the epilogue restores a PUSH2 a, b with POP2 b, a. As with PUSH2, the stack slot must be 16-byte aligned and neither register may be RSP; in addition the two registers must differ, or the instruction raises #UD. POP2P carries the push-pop acceleration hint and should match a PUSH2P.

Forms

Every encoding of POP2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`POP2 r64, r64` POP2_GPR64u64_GPR64u64_APX_N3	`EVEX.LLZ.NP.MAP4.W0 8F /0 ND=1`	APX_F + APX_NCI_NDD_NF

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n1 = dest1.number
n2 = dest2.number
if n1 == 4 or n2 == 4 or n1 == n2:
    fault(UD)                    # RSP, or one register twice
if rsp % 16 != 0:
    fault(GP, 0)
v1 = load(rsp, 64)
v2 = load(rsp + 8, 64)
rsp = rsp + 16
dest1.write(v1)                  # as POP dest1, then POP dest2
dest2.write(v2)

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`POP2 r64, r64`
`r64`	explicit	write
`r64`	explicit	write
`stack`	implicit	read
`rSP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: APX-EVEX-PP2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`APX_F_N3` APX	APX_F + APX_NCI_NDD_NF `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=29H,ECX=0):EBX[0]` APX_NCI_NDD_NF	Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions