x86-64.net

Instruction

POP2

APX instruction that pops two 64-bit registers from a 16-byte-aligned stack slot.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

POP2 a, b behaves like POP a followed by POP b, with a in the EVEX V field and b in ModRM.rm, so the epilogue restores a PUSH2 a, b with POP2 b, a. As with PUSH2, the stack slot must be 16-byte aligned and neither register may be RSP; in addition the two registers must differ, or the instruction raises #UD. POP2P carries the push-pop acceleration hint and should match a PUSH2P.

Forms

Every encoding of POP2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
POP2 r64, r64 POP2_GPR64u64_GPR64u64_APX_N3EVEX.LLZ.NP.MAP4.W0 8F /0 ND=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.