x86-64.net

Instruction

POP2P

POP2 with APX's push-pop acceleration hint, marking it as the partner of a PUSH2P so the processor can forward the values without the memory round trip.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of POP2P that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
POP2P r64, r64 POP2P_GPR64u64_GPR64u64_APX_N3EVEX.LLZ.NP.MAP4.W1 8F /0 ND=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.