POPA instruction (General-purpose)

POPA pops the eight general-purpose registers that PUSHA pushed: DI, SI and BP, then the slot of SP, which it skips, then BX, DX, CX and AX. The stack pointer is not loaded from the stack; it simply ends 16 bytes higher, or 32 with POPAD, past the whole frame. The operand size picks the width as it does for PUSHA, and the two mnemonics are one opcode, 61. No flag changes.

Since the saved SP is ignored, a handler that wants to return a value in a register writes it into that register’s slot of the frame before POPA: AX’s is the highest, 14 bytes above SP for POPA and 28 for POPAD. As for PUSHA, GNU as 2.44 and Clang 23 encode popa in 32-bit code as the 32-bit form and take popaw for the 16-bit one. A frame that starts or ends outside the stack segment raises #SS.

Not in 64-bit mode

Opcode 61 raises #UD in 64-bit mode, so the fixture has no case for POPA: the probe runs there and lists both forms as not run. 64-bit code restores registers with POP or APX’s POP2, and GNU as 2.44 and Clang 23 refuse popa there. AMD’s Zen 5 guide lists POPA as microcoded, without a latency.

Forms

Every encoding of POPA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`POPA` not in 64-bit mode POPA	`66 61`	Base instruction set
`POPAD` not in 64-bit mode POPAD	`61`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = OSIZE // 8                   # POPA: 2 bytes each; POPAD: 4
a = esp
rDI = load(a, OSIZE)
rSI = load(a + n, OSIZE)
rBP = load(a + 2 * n, OSIZE)     # the slot of ESP is skipped
rBX = load(a + 4 * n, OSIZE)
rDX = load(a + 5 * n, OSIZE)
rCX = load(a + 6 * n, OSIZE)
rAX = load(a + 7 * n, OSIZE)
esp = a + 8 * n

Not run on a processor: POPA does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`POPA` not in 64-bit mode `POPAD` not in 64-bit mode
`stack`	implicit	read
`rSP`	implicit	read, write
`AX, EAX`	implicit	write
`CX, ECX`	implicit	write
`DX, EDX`	implicit	write
`BX, EBX`	implicit	write
`BP, EBP`	implicit	write
`SI, ESI`	implicit	write
`DI, EDI`	implicit	write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I186` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`I386` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Not in 64-bit mode#