x86-64.net

Instruction

POPCNT

Counts the bits that are set in an operand; APX adds a form that leaves the flags unchanged.

Extensions
Forms
6 (2 Legacy, 4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of POPCNT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
POPCNT r16/32/64, m16/32/64 POPCNT_GPRv_MEMvF3 0F B8 /rPOPCNT
POPCNT r16/32/64, r16/32/64 POPCNT_GPRv_GPRvF3 0F B8 /rPOPCNT
POPCNT r16/32/64, r16/32/64 POPCNT_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 88 /rAPX_F + POPCNT
POPCNT r16/32/64, m16/32/64 POPCNT_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 88 /rAPX_F + POPCNT
POPCNT r16/32/64, r16/32/64 NF POPCNT_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 88 /r NF=1APX_F + APX_NCI_NDD_NF + POPCNT
POPCNT r16/32/64, m16/32/64 NF POPCNT_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 88 /r NF=1APX_F + APX_NCI_NDD_NF + POPCNT

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to POPCNT, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_popcnt_u32 int _mm_popcnt_u32(unsigned int __A)

POPCNT r16/32/64, r16/32/64 Legacy -mpopcnt

_mm_popcnt_u64 long long _mm_popcnt_u64(unsigned long long __A)

POPCNT r16/32/64, r16/32/64 Legacy -mpopcnt

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
POPCNT

POPCNT
CPUID.01H:ECX[23] POPCNT

Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2
APX_F_POPCNT

APX_F + POPCNT
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.01H:ECX[23] POPCNT

Nova Lake, Diamond Rapids
APX_F_POPCNT_N3

APX_F + APX_NCI_NDD_NF + POPCNT
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF
CPUID.01H:ECX[23] POPCNT

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.