POPP instruction (APX)

POPP is POP of a 64-bit register with a hint: the value it reads was written by a matching PUSHP. It does what POP does, loading the register from the top of the stack and raising RSP by 8, and changes no flag. Where the two are correctly paired, an APX processor can forward the value from the push without going through memory or relying on its store-forwarding predictor.

It is opcode 58+r under a REX2 prefix with W set, so it takes REX2 even for a register plain POP encodes in one byte, and it has no 16-bit form; the PUSHP page covers the encoding and the rule that both halves must be marked. POPP has the same exceptions as POP, plus #UD without APX. As with PUSHP, a hint that breaks the rule cannot change the result, only lose the speed-up. The POP form with a memory operand has no hinted version.

In our builds at -O2 with -mapxf, GCC 14 and Clang 23 restore saved registers in the epilogue with POPP and POP2P, mirroring the prologue’s PUSHP and PUSH2P: popp rbx, pop2p, pop2p, popp r15 in GCC’s function that saved six registers.

Forms

Every encoding of POPP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`POPP r64` POPP_GPR64	`REX2.W1 58+r`	APX_F

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = load(rsp, 64)                # POP with the hint that a PUSHP pushed
rsp = rsp + 8                    # what it pops (APX's PPX)
dest.write(v)

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`POPP r64`
`r64`	explicit	write
`stack`	implicit	read
`rSP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`APX_F` APX	APX_F `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F	Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions