POR instruction (MMX, SSE2)

POR is the bitwise OR of two 64-bit MMX or 128-bit XMM operands, with the result written over the first. VPOR covers its uses in vector code, merging fields and testing a whole array, and the VEX form; PAND covers what the legacy encodings share: the SSE2 XMM form, which leaves bits 128 and up of the register as they were (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes, and the MMX form with its x87 side effects. On Zen 5, the recorded por xmm8, xmmword ptr [mem] ORed 8000000000000000h into a zero quadword, and por mm1, qword ptr [mem] turned 8000000000000000h OR 1 into 8000000000000001h.

Intel’s Volume 3 table of exceptions for MMX instructions with a memory operand (Table 25-7) lists PAND, PANDN and PXOR but not POR, and no other table there names it, although POR’s own entry, like PAND’s, points to the section holding that table for its MMX form.

In baseline code

In our builds at -O2, for the x86-64 baseline and for -march=x86-64-v2, over fixed-size arrays:

Whole-array tests. Whether any uint32_t element is nonzero is POR of every vector into accumulators zeroed with PXOR, in GCC 14 and Clang 23. At the end, GCC folds the halves with PSRLDQ and POR and tests a doubleword in a general-purpose register; Clang compares with zero and uses MOVMSKPS at the baseline, and PTEST with x86-64-v2.
Combining fields. c[i] = a[i] | (b[i] << 8) from two byte arrays into uint16_t widens both, shifts one by 8 and ORs with POR, in GCC and, with x86-64-v2, in Clang. At the baseline Clang needs no OR: one PUNPCKLBW interleaves the bytes of the two arrays into the same words.
Selecting. With PAND and PANDN, POR completes the select under a compare mask that code before SSE4.1 uses instead of a blend.
The floating-point name. For a[i] = b[i] | c[i], whose result is only stored, Clang uses ORPS, a byte shorter, where GCC keeps POR.

AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle and four per cycle.

Forms

Every encoding of POR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`POR mm, m64` POR_MMXq_MEMq	`NP 0F EB /r`	MMX
`POR mm, mm` POR_MMXq_MMXq	`NP 0F EB /r`	MMX
`POR xmm, m128` POR_XMMdq_MEMdq	`66 0F EB /r`	SSE2
`POR xmm, xmm` POR_XMMdq_XMMdq	`66 0F EB /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1|b1, a0|b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

POR mm, mm/m64

i = 0
mm1.q[i] = mm1.q[i] | src2.q[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

POR xmm, xmm/m128

for i in range(2):
    xmm1.q[i] = xmm1.q[i] | src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`POR mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`POR xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

POR mm, mm/m64: none in XED
POR xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

POR mm, mm/m64: may abort a TSX transaction
POR xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to POR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_or_pd` `__m128d _mm_or_pd(__m128d __a, __m128d __b)`	`POR xmm, xmm` Legacy -msse2
`_mm_or_si128` `__m128i _mm_or_si128(__m128i __a, __m128i __b)`	`POR xmm, xmm` Legacy -msse2
`_mm_or_si64` `__m64 _mm_or_si64(__m64 __m1, __m64 __m2)`	`POR xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In baseline code#