PREFETCH instruction (PREFETCHW)

Forms

Every encoding of PREFETCH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PREFETCH m8` PREFETCH_EXCLUSIVE_MEMmprefetch	`0F 0D /0`	3DNowPrefetch
`PREFETCH m8` PREFETCH_RESERVED_0F0Dr4	`0F 0D /4`	3DNowPrefetch
`PREFETCH m8` PREFETCH_RESERVED_0F0Dr5	`0F 0D /5`	3DNowPrefetch
`PREFETCH m8` PREFETCH_RESERVED_0F0Dr6	`0F 0D /6`	3DNowPrefetch
`PREFETCH m8` PREFETCH_RESERVED_0F0Dr7	`0F 0D /7`	3DNowPrefetch

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # into the first-level data cache
# no fault for any address. 0F 0D /4 to /7, reserved, are PREFETCH
# too (AMD's manual), as is /2 on AMD's processors, which Intel's
# Xeon Phi took for PREFETCHWT1; with a register operand, #UD

Run on AMD Zen 5 (EPYC 9645): 15 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PREFETCH m8`
`m8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: memory operand only names cache lines

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PREFETCH_NOP` General-purpose PREFETCHW	3DNowPrefetch `CPUID.80000001H:ECX[8]` 3DNowPrefetch	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

PREFETCH