PREFETCHIT0

PREFETCHIT0 asks the processor to fetch the cache line of code that holds a byte into every level of the instruction-cache hierarchy, ahead of a jump or call to it. It is the code counterpart of PREFETCHT0: the same 0F 18 opcode with 7 in the ModRM reg field, a hint that changes no register, flag or memory, may be ignored and never faults. PREFETCHIT1, with 6 in the reg field, leaves the first-level cache out.

Only RIP-relative#

Both work only in 64-bit mode and only with a RIP-relative address, the next instruction’s address plus a 32-bit displacement; any other address, or a processor without them, makes them no-ops, so code can use them without checking CPUID leaf 7 subleaf 1 EDX bit 14 first. Intel advises pointing them at the first byte of an instruction. They came with Granite Rapids, and AMD’s guide for Zen 5 lists both, with the same levels as Intel’s entry (Table 8).

In compiled code#

At -O2 with -mprefetchi, Clang 23 compiles _m_prefetchit0(p) to PREFETCHIT0 with a RIP-relative address for a function or array of the same file, but also emits it through a register: for a pointer argument, and for an external function in position-independent code, whose address comes from the GOT. Those register forms are the no-ops just described. GCC 14 emitted the instruction only for a function of the same file, and for every other address dropped it with a warning that the prefetch would stay a NOP. AMD’s Zen 5 latency spreadsheet lists PREFETCHIT0 and PREFETCHIT1 as microcoded.

In the optimization guide

What the optimization guide says about PREFETCHIT0, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Redwood Cove

• Front end: Granite Rapids, not Meteor Lake, adds PREFETCHIT0 and PREFETCHIT1, which fetch code ahead of a jump to it: the first into every cache level, the second into all but the L1.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # IT0: code, into every level of the
                                 # caches
# only with a RIP-relative address, rip + disp32; otherwise, and on
# a processor without PREFETCHI, 0F 18 /7 is a hint NOP

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

memory operand only names cache lines

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PREFETCHIT0, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More PREFETCHI instructions

• PREFETCHIT1