PREFETCHIT1

PREFETCHIT1 asks the processor to fetch the cache line of code that holds a byte into the instruction-cache levels from the second level on, leaving the first-level cache out, ahead of a jump or call to it. It is the IT1 hint of the pair that PREFETCHIT0 describes, and the code counterpart of PREFETCHT1: 0F 18 with 6 in the ModRM reg field, a hint that changes no register, flag or memory and never faults. Like PREFETCHIT0 it acts only in 64-bit mode with a RIP-relative address and is a no-op otherwise and on processors that lack it (CPUID leaf 7 subleaf 1 EDX bit 14), so it needs no CPUID check. AMD’s guide for Zen 5 gives it the same levels as Intel’s entry: every instruction cache level but the L1 (Table 8).

In compiled code#

At -O2 with -mprefetchi, _m_prefetchit1(f) for a function f defined in the same file becomes prefetchit1 f[rip] in GCC 14 and Clang 23. For an external function GCC drops it with a warning, and Clang, in position-independent code, loads the address from the GOT and emits the register form, which is a no-op. AMD’s Zen 5 latency spreadsheet lists it as microcoded, with PREFETCHIT0.

In the optimization guide

What the optimization guide says about PREFETCHIT1, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Redwood Cove

• Front end: Granite Rapids, not Meteor Lake, adds PREFETCHIT0 and PREFETCHIT1, which fetch code ahead of a jump to it: the first into every cache level, the second into all but the L1.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # IT1: code, into every level but the
                                 # first
# only with a RIP-relative address, rip + disp32; otherwise, and on
# a processor without PREFETCHI, 0F 18 /6 is a hint NOP

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

memory operand only names cache lines

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PREFETCHIT1, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More PREFETCHI instructions

• PREFETCHIT0