PREFETCHNTA instruction (SSE)

PREFETCHNTA asks for the cache line holding a byte to be brought close to the processor while disturbing the caches as little as possible: it is the hint for data that will be read once and then not again soon. Like PREFETCHT0, whose page covers what all four hints share, it is only a hint, changes nothing a program can see and never faults; on Zen 5 it ran without an exception for an unmapped address near 0 and for a kernel address.

Where the line goes

What “as little as possible” means differs between processors, and the vendors’ guides describe it:

On Intel’s Core 2 and Atom processors and those based on Skylake, the line is filled into the L1 cache but not the L2; on the Xeon Scalable processors it also goes into the L3, in a position chosen early for replacement (Intel’s optimization manual, Tables 9-1 to 9-3).
AMD’s Zen 5 guide says a line filled into the L2 cache by PREFETCHNTA is marked for early eviction from the L2 and, when evicted, is not put into the L3 (Section 2.6.4).

Either way the line skips part of the hierarchy, so data prefetched with NTA and then needed again is fetched from farther away than after PREFETCHT0.

When to use it

Intel’s manual suggests NTA for single-pass algorithms, which pass each piece of data once through the whole computation, and T0 for multi-pass ones that come back to a batch of data in several stages (Section 9.1). The same guidelines recommend the streaming stores, such as MOVNTDQ, to keep data that is written and not read again from disturbing the caches.

From C

_mm_prefetch(p, _MM_HINT_NTA) and __builtin_prefetch(p, 0, 0), a locality of 0, give PREFETCHNTA with GCC 14 and Clang 23 at -O2; so does __builtin_prefetch(p, 1, 0) unless PREFETCHW is enabled. Neither compiler removes redundant prefetches: in a loop that sums an array of long with a prefetch 64 elements ahead, both issue one PREFETCHNTA per element, eight per line, Clang four per unrolled iteration.

AMD’s Zen 5 instruction table lists PREFETCHNTA, like the T0 to T2 hints, as microcoded.

In the optimization guide

What the optimization guide says about PREFETCHNTA, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Software prefetch: A prefetch instruction asks for the 64-byte line holding its address and changes nothing a program can see.
Software prefetch: Each core decides which caches each prefetch hint fills, and Intel’s and AMD’s cores differ. sources differ
Software prefetch: Software prefetch pays where the hardware cannot see the pattern and the data is not in the cache already.

Bulldozer to Excavator

Loads, stores and caches: PREFETCHT0, T1 and T2 all fill the L1, like PREFETCH, and PREFETCHW fills it for writing.

Zen and Zen+

Loads, stores and caches: Hardware prefetchers fill the L1 instruction and data caches and the L2, and Agner Fog found them better than software prefetching in most cases.

Zen 2

Loads, stores and caches: Hardware prefetchers fill the L1 instruction and data caches and the L2, and Agner Fog found them better than software prefetching in most cases.

Zen 3

Loads, stores and caches: The L1 prefetchers follow sequential lines up or down, a constant stride per instruction, and recurring patterns within a region; the L2 ones follow sequential lines and fetch the line before or after.

Zen 4

Loads, stores and caches: The L1 prefetchers follow sequential lines up or down, a constant stride per instruction, and recurring patterns within a region; the L2 ones follow sequential lines and fetch the adjacent line.

Zen 5

Loads, stores and caches: PREFETCHT0 fills every data cache level, PREFETCHT1 all but the L1, and PREFETCHT2 all but the L1 and L2. sources differ

Forms

Every encoding of PREFETCHNTA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PREFETCHNTA m8` PREFETCHNTA_MEMmprefetch	`0F 18 /0`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # NTA: close to the processor, where
                                 # it disturbs the caches least: for
                                 # data used once
# no fault for any address; prefetches from uncacheable or
# write-combining memory are dropped (Intel's manual)

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PREFETCHNTA m8`
`m8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: non-temporal hint; memory operand only names cache lines

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE_PREFETCH` SSE	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Where the line goes#

When to use it#

From C#