PREFETCHRST2

PREFETCHRST2 brings the cache line that holds a byte closer to the core, as PREFETCHT0 and its siblings do, but with the read-shared hint of MOVRS: this core and at least one other are expected to read the line before anyone writes it. Where the line goes is the processor’s choice, picked for reading through the shared cache levels; the VMOVRSD page says what the hint changes in the caches and what a later write may cost. Like the other prefetches it is only a hint: it changes no register, flag or memory, may be ignored, and raises no fault for any address, only #UD with a LOCK prefix. When it acts it fetches at least 32 bytes, and it skips uncacheable and write-combining memory.

Order#

Intel’s entry orders PREFETCHRST2 only against serializing instructions such as CPUID and WRMSR. Fences, locked instructions, CLFLUSH, CLFLUSHOPT and other prefetches may pass it, since the processor may fetch such lines speculatively at any time anyway, and the instruction only hints at that.

Encoding and older processors#

The encoding is 0F 18 with 4 in the ModRM reg field and a memory operand, next to PREFETCHT0’s 1 and PREFETCHT2’s 3, and it works the same in every mode, where MOVRS exists only in 64-bit mode. The ISE’s exception list has no #UD for a processor without MOVRS, only the one for LOCK. Zen 5, whose CPUID.(EAX=07H,ECX=1):EAX[31] is clear, has no MOVRS, and the probe recorded the same bytes on it as a NOP form, 0F 18 /4 with a memory operand: at each operand size they ran without a fault and changed nothing. Intel lists MOVRS, and PREFETCHRST2 with it, for Diamond Rapids and Nova Lake.

In our builds#

GCC 14.2.0 has no -mmovrs. Clang 23.1.2 with -mmovrs, or with -march=diamondrapids, compiles _m_prefetchrs(p) to prefetchrst2 byte ptr [rdi], 0F 18 27, and the address of a global array to the RIP-relative form. The intrinsic’s name is not the instruction’s, and __builtin_prefetch never emits PREFETCHRST2: its localities give PREFETCHNTA to PREFETCHT0, as without MOVRS. GNU as 2.44 assembles the mnemonic to the same bytes.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # into caches chosen for lines that
                                 # several cores will read before any
                                 # writes them (MOVRS's read-shared
                                 # hint); a write before that is only
                                 # slower
# no fault for any address; on a processor without MOVRS, 0F 18 /4
# is a hint NOP

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

LEGACY-PREFETCH

Attributes

What else XED records about the forms. How to read.

All forms

memory operand only names cache lines

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PREFETCHRST2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More MOVRS instructions

• MOVRS
• VMOVRSB
• VMOVRSD
• VMOVRSQ
• VMOVRSW