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Instruction

PREFETCHRST2

Prefetches data with a hint that several cores are likely to read it before it is written, into caches chosen for read sharing.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of PREFETCHRST2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
PREFETCHRST2 m8 PREFETCHRST2_MEMu80F 18 /4MOVRS

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
MOVRS

MOVRS
CPUID.(EAX=07H,ECX=1):EAX[31] MOVRS

Nova Lake, Diamond Rapids

More MOVRS instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.