PREFETCHT0 instruction (SSE)

PREFETCHT0 asks the processor to bring the cache line holding a byte into every level of the cache, so that a load a little later finds it there. It is a hint: it changes no register, flag or memory, the processor may ignore it, and it never faults. On Zen 5 it ran without an exception for an unmapped address near 0 and for a kernel address; a load from either would have raised #PF. PREFETCHT1, PREFETCHT2 and PREFETCHNTA are the same instruction with other hints in the ModRM reg field, and PREFETCHW asks for the line in a state ready for a write.

From C

GCC 14 and Clang 23 emit PREFETCHT0 for __builtin_prefetch(p), whose default locality is 3, and for _mm_prefetch(p, _MM_HINT_T0); localities 2, 1 and 0 give T1, T2 and NTA. A prefetch for writing, __builtin_prefetch(p, 1), also becomes PREFETCHT0 unless PREFETCHW is enabled, with -mprfchw for example; -march=x86-64-v3 does not enable it.

Choosing the hint

Intel’s optimization manual suggests PREFETCHT0 for data that a program will pass over several times and PREFETCHNTA for data used once (Section 9.1). A prefetch helps only when it is issued early enough to cover the time memory takes, and not so early that the line is evicted again before the load.

What the hints do on AMD

AMD’s general-purpose manual says that AMD processors treat T1 and T2 as T0. AMD’s Zen 5 guide describes them differently for Zen 5: T0 fills every level, T1 every level but the L1 cache, T2 the L3 cache only (Table 8). The guide’s instruction table lists PREFETCHT0, T1, T2 and NTA as microcoded, while AMD’s own PREFETCH and PREFETCHW are single macro-ops.

PREFETCHT0 belongs to SSE, which every x86-64 processor has; prefetches from uncacheable or write-combining memory are dropped.

In the optimization guide

What the optimization guide says about PREFETCHT0, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Software prefetch: A prefetch instruction asks for the 64-byte line holding its address and changes nothing a program can see.
Software prefetch: Each core decides which caches each prefetch hint fills, and Intel’s and AMD’s cores differ. sources differ
Software prefetch: Software prefetch pays where the hardware cannot see the pattern and the data is not in the cache already.

Jaguar and Puma

Loads, stores and caches: Hardware prefetchers fill the L1 instruction cache, the L1 data cache and the L2, and GCC turns on software prefetching at -O3 for these cores, though AMD’s spreadsheet gives PREFETCHT0 and its kin no timing. sources differ

Zen 5

Loads, stores and caches: PREFETCHT0 fills every data cache level, PREFETCHT1 all but the L1, and PREFETCHT2 all but the L1 and L2. sources differ

Forms

Every encoding of PREFETCHT0 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PREFETCHT0 m8` PREFETCHT0_MEMmprefetch	`0F 18 /1`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # T0: into every level of the caches
# no fault for any address; prefetches from uncacheable or
# write-combining memory are dropped (Intel's manual)

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PREFETCHT0 m8`
`m8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: memory operand only names cache lines

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE_PREFETCH` SSE	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

From C#

Choosing the hint#

What the hints do on AMD#