PREFETCHT1 instruction (SSE)

In the optimization guide

What the optimization guide says about PREFETCHT1, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Software prefetch: A prefetch instruction asks for the 64-byte line holding its address and changes nothing a program can see.
Software prefetch: Each core decides which caches each prefetch hint fills, and Intel’s and AMD’s cores differ. sources differ
Software prefetch: Software prefetch pays where the hardware cannot see the pattern and the data is not in the cache already.

Zen 5

Loads, stores and caches: PREFETCHT0 fills every data cache level, PREFETCHT1 all but the L1, and PREFETCHT2 all but the L1 and L2. sources differ

Forms

Every encoding of PREFETCHT1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PREFETCHT1 m8` PREFETCHT1_MEMmprefetch	`0F 18 /2`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # T1: into the second level and up;
                                 # AMD's processors take it as T0
# no fault for any address

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PREFETCHT1 m8`
`m8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: memory operand only names cache lines

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE_PREFETCH` SSE	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions