PREFETCHW

PREFETCHW brings the cache line holding a byte close to the core in a state that lets a store write it at once: other caches give up their copies, as they would for a write. Without it, the first store to a line that is not cached, or that another core holds, waits for that exchange, the read for ownership; Intel’s optimization manual suggests PREFETCHW shortly before such stores for that reason (Section 20.13.1.4). Like PREFETCHT0, it is a hint that changes no register, flag or memory and never faults: Zen 5 ran it without an exception at an unmapped address near 0 and at a kernel address.

A hint with one visible trace#

AMD’s manual allows PREFETCHW on a writable page to set the dirty bit of its page table entry, as a store would; a load, or CLFLUSH, sets only the accessed bit. Intel’s manual orders PREFETCHW with nothing but serializing instructions such as CPUID: fences, locked instructions and flushes may pass it. It also drops prefetches from memory that is not write-back.

From C#

GCC 14 and Clang 23 emit PREFETCHW for __builtin_prefetch(p, 1) and for _m_prefetchw(p) only when the target has it: with -mprfchw, or -march=broadwell, skylake, znver1 and later. With -march=haswell or x86-64-v4, both become PREFETCHT0.

Where the opcode comes from#

0F 0D is AMD’s, from 3DNow!: the ModRM reg field picks PREFETCH (/0) or PREFETCHW (/1), /2 is PREFETCHWT1 on Intel’s Xeon Phi, and AMD’s manual makes the other values act as PREFETCH. XED decodes /3 as PREFETCHW; for a hint the two cannot be told apart. The CPUID bit is leaf 80000001H, ECX bit 8, which Intel calls PREFETCHW and AMD 3DNowPrefetch; AMD’s manual counts long mode as enough on its own processors, and Intel’s optimization manual names Broadwell as Intel’s first core with the instruction (Table 9-3).

What it fills#

AMD’s Zen 5 guide puts the line into the L1 data cache, trying for an exclusive state (Table 8), and lists PREFETCHW as one macro-op. By Intel’s optimization manual it fills L1 and L2 on Skylake, and L3 and the snoop filter as well on Xeon Scalable processors (Tables 9-2 and 9-3).

In the optimization guide

What the optimization guide says about PREFETCHW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

• Loads, stores and caches: PREFETCHT0, T1 and T2 all fill the L1, like PREFETCH, and PREFETCHW fills it for writing.

Haswell and Broadwell

• What Broadwell changed: Broadwell adds ADCX and ADOX, RDSEED and PREFETCHW, which -march=broadwell enables in LLVM; code built that way can fault on Haswell, which has none of them.

Silvermont to Goldmont Plus

• Loads, stores and caches: From Silvermont on, prefetchw fetches a line for writing, so that stores to it complete sooner.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # into the first-level data cache,
                                 # ready to be written: the line is
                                 # taken as for a write, and the page's
                                 # dirty bit may be set (AMD's manual)
# no fault for any address. 0F 0D /3 is PREFETCHW too

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

memory operand only names cache lines

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More PREFETCHW instructions

• NOP
• PREFETCH