PREFETCHWT1 instruction (PREFETCHWT1)

PREFETCHWT1 is PREFETCHW with a T1 hint: it asks for the cache line holding a byte in a state that a store can write at once (the request for ownership that a write would make), but into the second-level cache rather than the first, for data that will be written a little later. Like every prefetch, it is only a hint: no register, flag or memory changes, no fault for any address, and nothing is fetched from uncacheable or write-combining memory.

A Xeon Phi instruction

Intel documents it in the part of its manual reserved for the Xeon Phi processors, and its CPUID bit, leaf 7, ECX bit 0, is reported by Knights Landing and Knights Mill only, as the table of processors shows; Zen 5 does not report it either, so the probe did not run it.

Its bytes are another matter. 0F 0D /2 sits in AMD’s prefetch group, where /0 is PREFETCH and /1 PREFETCHW, and AMD’s manual makes every reserved value of the ModRM reg field act as PREFETCH. On an AMD processor, PREFETCHWT1 therefore runs as a plain read prefetch into the first-level cache instead of faulting.

From C

GCC 14 at -O2 emits it for _mm_prefetch(p, _MM_HINT_ET1), and for __builtin_prefetch(p, 1, n) with a locality n of 0, 1 or 2, when compiling with -mprefetchwt1 or -march=knl; locality 3 stays PREFETCHW. Without the option, all of them become PREFETCHW (with -mprfchw) or one of the read prefetches. Clang 23 no longer has the option at all: with -march=knl it emits PREFETCHW for every one of them.

Forms

Every encoding of PREFETCHWT1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PREFETCHWT1 m8` PREFETCHWT1_MEMu8	`0F 0D /2`	PREFETCHWT1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # T1, ready to be written: into the
                                 # second level and up
# no fault for any address. Only Intel's Xeon Phi processors report
# it; AMD's run 0F 0D /2 as PREFETCH

Not run on a processor: the Zen 5 guest that ran the probe does not report PREFETCHWT1 in CPUID.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PREFETCHWT1 m8`
`m8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: memory operand only names cache lines

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PREFETCHWT1` PREFETCHWT1	PREFETCHWT1 `CPUID.(EAX=07H,ECX=0):ECX[0]` PREFETCHWT1	Knights Landing, Knights Mill

A Xeon Phi instruction#

From C#