PSADBW instruction (SSE, SSE2)

PSADBW takes two vectors of unsigned bytes, works out the absolute difference of every pair, and adds the differences in groups of eight. Each group’s total, at most 2040 (8 times 255), lands in the low word of the group’s quadword, and the rest of that quadword is cleared, so an XMM register comes out holding two small 64-bit numbers and an MMX register one.

Sum of absolute differences

The name says what it was made for: comparing two blocks of pixels, the inner step of motion estimation in video encoders, where a smaller sum means a closer match. Intel’s optimization manual describes it this way for 4x4 to 8x8 blocks (Section 6.6.9) and points to MPSADBW of SSE4.1, which computes eight sums of four bytes at shifting offsets, and PHMINPOSUW, which finds the smallest word, as the better pair for that search (Section 6.6.10).

Compilers recognize the pattern in plain C. For s += abs(p[i] - q[i]) over uint8_t arrays, GCC 14 at -O2 emits PSADBW on 16 bytes at a time and adds the results with PADDD when the trip count is a constant, and keeps a loop with a variable count scalar. Clang 23 also uses PSADBW but feeds it only four bytes at a time for the SSE2 baseline, padded with zeros, and eight with -mavx2.

Against zero

With a zeroed register as the other operand, each difference is the byte itself, and PSADBW becomes a horizontal sum of eight bytes per quadword that cannot overflow. That makes it the last step of counting bits in a vector: after a byte-wise count, Clang 23 at -O2 compiles __builtin_popcountll over a uint64_t array (without POPCNT) to bit-twiddling on bytes and one PSADBW against zero per vector, which leaves each quadword’s count in place. The same trick sums any byte array, eight bytes per quadword, though neither GCC 14 nor Clang 23 uses it for a plain s += p[i] loop; both widen the bytes with unpacks instead.

MMX, SSE2 and AVX-512

The MMX form came with SSE, not with MMX, and the XMM form with SSE2. The legacy XMM form needs a memory operand aligned to 16 bytes. VPSADBW is the VEX and EVEX form, one sum per quadword at every width, and AVX-512BW adds VDBPSADBW, which sums groups of four bytes against shuffled positions.

Forms

Every encoding of PSADBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSADBW mm, m64` PSADBW_MMXq_MEMq	`NP 0F F6 /r`	SSE
`PSADBW mm, mm` PSADBW_MMXq_MMXq	`NP 0F F6 /r`	SSE
`PSADBW xmm, m128` PSADBW_XMMdq_MEMdq	`66 0F F6 /r`	SSE2
`PSADBW xmm, xmm` PSADBW_XMMdq_XMMdq	`66 0F F6 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Groups of 8 adjacent bytes are combined into one quadword.

Result quadword i comes from bytes 8i to 8i+7 of xmm1 and xmm2. Result quadwords 1 to 0: sum, sum.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSADBW mm, mm/m64

i = 0
x = 0
for j in range(8 * i, 8 * i + 8):
    x += abs(mm1.b[j] - src2.b[j])
mm1.q[i] = x
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSADBW xmm, xmm/m128

for i in range(2):
    x = 0
    for j in range(8 * i, 8 * i + 8):
        x += abs(xmm1.b[j] - src2.b[j])
    xmm1.q[i] = x
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSADBW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSADBW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSADBW mm, mm/m64: mmx-mem
PSADBW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSADBW mm, mm/m64: may abort a TSX transaction
PSADBW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSADBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sad_epu8` `__m128i _mm_sad_epu8(__m128i __a, __m128i __b)`	`PSADBW xmm, xmm` Legacy -msse2
`_mm_sad_pu8` `__m64 _mm_sad_pu8(__m64 __a, __m64 __b)`	`PSADBW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

Sum of absolute differences#

Against zero#

MMX, SSE2 and AVX-512#