PSHUFB

PSHUFB picks bytes by index. Each byte of the second operand selects which byte of the first operand goes to its position in the result, and a selector with bit 7 set writes zero there instead. Only the low four bits of a selector count (three in the MMX form), so 10h selects byte 0 rather than giving zero. Because the selectors come from a register and not from an immediate, one instruction applies any byte permutation, chosen at run time or loaded from a table. In the intrinsic _mm_shuffle_epi8(a, b), a holds the data and b the selectors.

It turns up in three roles:

• Fixed rearrangements, with a constant selector vector: reversing the order of the 16 bytes (the byte-order swap of a whole vector, which Intel’s optimization manual uses in a reverse memory copy), gathering the bytes of interest to one end, or spreading them out.
• Broadcasting a byte. All-zero selectors copy byte 0 everywhere. Compiling for SSSE3, GCC 14 and Clang 23 at -O2 turn _mm_set1_epi8(c) into MOVD, PXOR and PSHUFB; AVX2 has VPBROADCASTB for this.
• Table lookup. With a table of 16 bytes as the data and values of 0 to 15 as selectors, PSHUFB looks up 16 entries at once. Splitting each byte into its low and high halves (a shift, and an AND with 0Fh) gives two lookups that together cover all 256 byte values; vector bit counting, hexadecimal conversion and character classification can be built this way.

The legacy form with a memory operand needs it aligned to 16 bytes. The VEX and EVEX forms, VPSHUFB, work within each 128-bit lane: a 256-bit shuffle cannot move a byte from one half of the register to the other, and each half needs its own copy of a lookup table. VPERMB of AVX512_VBMI permutes bytes across a whole register.

In the optimization guide

What the optimization guide says about PSHUFB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

• Front end: Silvermont decodes SSSE3 and SSE4 instructions that use xmm8 to xmm15 slowly, as they exceed 3 bytes of prefixes and escapes. sources differ
• Vectors and cryptography: pshufb, pmulld, paddq and psubq are slow on Silvermont and much faster from Goldmont on.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = mm1.read()  # mm1 as it was
for i in range(8):
    x = src2.b[i]
    if x & 0x80:
        mm1.b[i] = 0
    else:
        mm1.b[i] = src1.b[x & 7]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

src1 = xmm1.read()  # xmm1 as it was
for i in range(16):
    x = src2.b[i]
    if x & 0x80:
        xmm1.b[i] = 0
    else:
        xmm1.b[i] = src1.b[x & 15]
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSHUFB mm, mm/m64

mmx-mem

PSHUFB xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSHUFB mm, mm/m64

may abort a TSX transaction

PSHUFB xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSHUFB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSIGNB
• PSIGND
• PSIGNW