PSHUFD instruction (SSE2)

PSHUFD copies the four doublewords of its source to the destination in an order that the immediate gives: bits 1:0 choose the source element for result element 0, bits 3:2 for element 1, and so on up to bits 7:6 for element 3. An element may be chosen more than once or not at all. Unlike most legacy SSE instructions, PSHUFD does not read its destination, so it also serves as a copy that rearranges on the way.

The intrinsics headers build the immediate with _MM_SHUFFLE(d, c, b, a), which puts the index for element 3 first. Some immediates come up again and again (a0 to a3 are the source’s elements):

imm8	Result, element 3 to 0	Use
00h	a0 a0 a0 a0	broadcast element 0
1Bh	a0 a1 a2 a3	reverse the elements
4Eh	a1 a0 a3 a2	swap the 64-bit halves
B1h	a2 a3 a0 a1	swap neighboring elements
EEh	a3 a2 a3 a2	move the high half down

Compiling for SSE2, GCC 14 and Clang 23 at -O2 turn _mm_set1_epi32(x) into MOVD and PSHUFD with 00h. Adding a vector to its 4Eh shuffle, and the sum to its B1h shuffle, leaves the total of all four elements in every element, a common last step of a vectorized sum; Clang ends its own integer reductions this way, with EEh and 55h.

The legacy form with a memory operand needs it aligned to 16 bytes. PSHUFLW and PSHUFHW do the same for the four words of one half, and SHUFPS takes two elements from each of two sources. The VEX and EVEX forms, VPSHUFD, apply the immediate to each 128-bit lane separately; VPERMD moves doublewords across lanes.

Forms

Every encoding of PSHUFD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSHUFD xmm, m128, imm8` PSHUFD_XMMdq_MEMdq_IMMb	`66 0F 70 /r ib`	SSE2
`PSHUFD xmm, xmm, imm8` PSHUFD_XMMdq_XMMdq_IMMb	`66 0F 70 /r ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: two bits of imm8 per result doubleword pick one of the four doublewords of the source.

Example: imm8 = 0x61 (0110 0001 in binary).

With imm8 = 0x61, result doublewords 3 to 0: a1, a2, a0, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    j = imm8 >> 2 * i & 3
    xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSHUFD xmm, xmm/m128, imm8`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSHUFD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_shuffle_epi32` `__m128i _mm_shuffle_epi32(__m128i a, const int imm)`	`PSHUFD xmm, xmm, imm8` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions