PSHUFHW instruction (SSE2)

PSHUFHW rearranges the four words of the high quadword of its source and copies the low quadword through unchanged, the mirror image of PSHUFLW. Its immediate counts within the high half: bits 1:0 choose which of words 4 to 7 lands in word 4, and so on up to bits 7:6 for word 7, so the same immediate means the same arrangement in either instruction. A word may be chosen more than once, the destination is not read, and the intrinsic is _mm_shufflehi_epi16(v, imm).

On its own it reverses or rotates the high four words; most often it works in a pair or a trio with PSHUFLW and PSHUFD, since SSE2 has no instruction that moves words freely across the whole register (see PSHUFLW). Examples from GCC 14 and Clang 23 at -O2 for the SSE2 baseline, written with GCC’s __builtin_shuffle and Clang’s __builtin_shufflevector:

Swapping neighboring words, the same arrangement in both halves: both compilers emit PSHUFLW B1h and PSHUFHW B1h.
Broadcasting word 5: Clang emits PSHUFHW 55h, which copies word 5 into words 4 to 7, then PSHUFD EEh, which copies the high quadword down, the two-step broadcast that Intel’s optimization manual shows (Section 6.4.11). GCC uses PUNPCKHWD of the register with itself and PSHUFD 55h.
Reversing the high half alone is one PSHUFHW 1Bh in both.

The legacy form reads all 16 bytes of a memory operand, which must be aligned to 16. With SSSE3, a PSHUFB with a table can do any of these at once: reversing all eight words, which Clang does with PSHUFD, PSHUFLW and PSHUFHW for SSE2, is one PSHUFB in both compilers with -mssse3. The VEX and EVEX forms, VPSHUFHW, apply the immediate to the high quadword of each 128-bit lane, and the EVEX form can mask words.

Forms

Every encoding of PSHUFHW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSHUFHW xmm, m128, imm8` PSHUFHW_XMMdq_MEMdq_IMMb	`F3 0F 70 /r ib`	SSE2
`PSHUFHW xmm, xmm, imm8` PSHUFHW_XMMdq_XMMdq_IMMb	`F3 0F 70 /r ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: two bits of imm8 per word pick each of the high four words from the high four; the low four are copied.

Example: imm8 = 0x1B (0001 1011 in binary).

With imm8 = 0x1B, result words 7 to 0: a4, a5, a6, a7, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k if i % 8 >= 4 else i  # the low four copied
    xmm1.w[i] = src2.w[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSHUFHW xmm, xmm/m128, imm8`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSHUFHW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_shufflehi_epi16` `__m128i _mm_shufflehi_epi16(__m128i a, const int imm)`	`PSHUFHW xmm, xmm, imm8` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions