PSHUFLW instruction (SSE2)

PSHUFLW rearranges the four words of the low quadword of its source as an immediate says and copies the high quadword through unchanged; PSHUFHW is its mirror image. The immediate works as PSHUFD’s does, two bits per result word: bits 1:0 choose the source word for word 0, and so on up to bits 7:6 for word 3, and a word may be chosen more than once. The intrinsic is _mm_shufflelo_epi16(v, imm), with the immediate usually built by _MM_SHUFFLE. Like PSHUFD, it does not read its destination, so it copies as it shuffles.

Word shuffles in SSE2

SSE2 has no single instruction that moves words anywhere in a register (SSSE3’s PSHUFB does, with a table of byte indices), so word arrangements are put together from PSHUFLW, PSHUFHW and PSHUFD. Intel’s optimization manual notes that at most three of them cover the common cases, and shows a broadcast and a reversal (Section 6.4.11). GCC 14 and Clang 23 at -O2, compiling for the SSE2 baseline:

Broadcast. Clang turns _mm_set1_epi16(x) into MOVD, PSHUFLW 00h, which fills the low four words, and PSHUFD 44h, which copies the low quadword up; it keeps that sequence with -mssse3. GCC uses PUNPCKLWD of the register with itself and PSHUFD 00h, and with -mssse3 a PSHUFB from a table. With AVX2 the job is VPBROADCASTW’s.
Reversal. To reverse eight uint16_ts, Clang swaps the quadwords with PSHUFD 4Eh and reverses each half with PSHUFLW 1Bh and PSHUFHW 1Bh. GCC instead loads each half with MOVQ, reverses it with one PSHUFLW 1Bh and stores it at the other end. With -mssse3 both use a single PSHUFB.

The legacy form reads all 16 bytes of a memory operand, which must be aligned to 16. PSHUFW is the MMX instruction for a 64-bit register. The VEX and EVEX forms, VPSHUFLW, shuffle the low quadword of each 128-bit lane with the same immediate, and the EVEX form can mask words.

Forms

Every encoding of PSHUFLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSHUFLW xmm, m128, imm8` PSHUFLW_XMMdq_MEMdq_IMMb	`F2 0F 70 /r ib`	SSE2
`PSHUFLW xmm, xmm, imm8` PSHUFLW_XMMdq_XMMdq_IMMb	`F2 0F 70 /r ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: two bits of imm8 per word pick each of the low four words from the low four; the high four are copied.

Example: imm8 = 0x1B (0001 1011 in binary).

With imm8 = 0x1B, result words 7 to 0: a7, a6, a5, a4, a0, a1, a2, a3.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k if i < 4 else i  # the high four copied
    xmm1.w[i] = src2.w[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSHUFLW xmm, xmm/m128, imm8`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSHUFLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_shufflelo_epi16` `__m128i _mm_shufflelo_epi16(__m128i a, const int imm)`	`PSHUFLW xmm, xmm, imm8` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Word shuffles in SSE2#