PSHUFW instruction (SSE)

Forms

Every encoding of PSHUFW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSHUFW mm, m64, imm8` PSHUFW_MMXq_MEMq_IMMb	`NP 0F 70 /r ib`	SSE
`PSHUFW mm, mm, imm8` PSHUFW_MMXq_MMXq_IMMb	`NP 0F 70 /r ib`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: two bits of imm8 per result word pick one of the four words of the source.

Example: imm8 = 0x61 (0110 0001 in binary).

With imm8 = 0x61, result words 3 to 0: a1, a2, a0, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    j = imm8 >> 2 * i & 3
    mm1.w[i] = src2.w[j]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSHUFW mm, mm/m64, imm8`
`mm`	explicit	write
`mm/m64`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: mmx-mem

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions