PSIGNB

PSIGNB applies the sign of one vector of bytes to another: for each pair, it negates the destination byte if the source byte is negative, clears it to zero if the source byte is zero, and leaves it unchanged if the source byte is positive. PSIGNW and PSIGND do the same for words and doublewords. SSSE3 added all three, with PABSB and its kin, in both an MMX form (8 bytes) and an XMM one (16 bytes, destructive, the second operand an XMM register or an aligned 128-bit memory location).

On Zen 5, the recorded psignb xmm12, xmmword ptr [mem] turned byte 01h of the destination into 00h where the matching source byte was 00h, FFh into 01h and 01h into FFh where the matching source bytes were FFh (negative), and left 7Fh, 80h and the rest unchanged where the source bytes were positive. Negating 80h itself left it 80h: -128 has no positive byte counterpart, the same edge PABSB’s page describes.

Three ways, not two#

Applying a value’s own sign to itself is abs; applying another array’s sign is c[i] < 0 ? -b[i] : (c[i] == 0 ? 0 : b[i]). Neither GCC 14 nor Clang 23, in our builds at -O2 over fixed-size int8_t arrays, folds that plain C into PSIGNB, even with -march=x86-64-v2: both negate a copy with PSUBB, build a mask of the zero elements with PCMPEQB and PANDN, and choose between the negated and the original byte by the sign operand’s own sign bit, with PBLENDVB. At the baseline, without PBLENDVB, they combine the same three pieces with PAND, PANDN and POR instead. A two-way choice such as the unsigned minimum compiles to one instruction, as PMINUB’s page shows; this three-way choice stays several in both compilers, with or without SSSE3.

AMD’s latency spreadsheet for Zen 5 gives PSIGNB one macro-op with a latency of two cycles and a throughput of two, on two of the four vector pipelines, for both the MMX and the XMM form.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    a = mm1.b[i]
    b = src2.b[i]
    sb = src2.sb[i]
    if sb < 0:
        mm1.b[i] = -a
    elif b == 0:
        mm1.b[i] = 0
    else:
        mm1.b[i] = a
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

for i in range(16):
    a = xmm1.b[i]
    b = src2.b[i]
    sb = src2.sb[i]
    if sb < 0:
        xmm1.b[i] = -a
    elif b == 0:
        xmm1.b[i] = 0
    else:
        xmm1.b[i] = a
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSIGNB mm, mm/m64

mmx-mem

PSIGNB xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSIGNB mm, mm/m64

may abort a TSX transaction

PSIGNB xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSIGNB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGND
• PSIGNW