PSIGND

PSIGND applies the sign of each source doubleword to the matching destination doubleword: negated for a negative source, cleared for zero, unchanged for a positive one, four elements in an XMM register and two in an MMX one. PSIGNB covers the family and its SSSE3 history. The negation wraps: on Zen 5, the recorded psignd xmm0, xmmword ptr [mem] left 80000000h as 80000000h where the source element was negative, as PABSD does with the same value, and kept 7FFFFFFFh and 0000000Fh under positive source elements; it left bits 511:128 of XMM0 as they were (see mixing SSE and AVX).

In compiled code#

In our builds at -O2 with -mssse3, neither GCC 14 nor Clang 23 derives PSIGND from C, and both keep it exactly as written when it comes from _mm_sign_epi32:

• _mm_sign_epi32(x, x) stays PSIGND, not PABSD, and _mm_sign_epi32(x, _mm_set1_epi32(-1)) becomes PCMPEQD and PSIGND, where a negation would otherwise be a PSUBD from zero.
• A two-way conditional negation, e[i] < 0 ? -d[i] : d[i] over int32_t arrays, is a sign mask from PCMPGTD in both; Clang applies it with PXOR and PSUBD, GCC selects between the value and its negation with PAND, PANDN and POR.
• Multiplying by the sign, d[i] * ((e[i] > 0) - (e[i] < 0)), stays a multiplication: two PCMPGTD and a PSUBD build -1, 0 or 1, then PMULUDQ pairs, or VPMULLD with -mavx2.

AMD’s latency spreadsheet for Zen 5 gives PSIGND one macro-op with a latency of two cycles and two per cycle, on pipes FP0 and FP3, the same as PSIGNB and PSIGNW. The XMM form’s memory operand must be aligned to 16 bytes; VPSIGND is the VEX form, and AVX-512 has no sign instructions.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = mm1.d[i]
    b = src2.d[i]
    sb = src2.sd[i]
    if sb < 0:
        mm1.d[i] = -a
    elif b == 0:
        mm1.d[i] = 0
    else:
        mm1.d[i] = a
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

for i in range(4):
    a = xmm1.d[i]
    b = src2.d[i]
    sb = src2.sd[i]
    if sb < 0:
        xmm1.d[i] = -a
    elif b == 0:
        xmm1.d[i] = 0
    else:
        xmm1.d[i] = a
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSIGND mm, mm/m64

mmx-mem

PSIGND xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSIGND mm, mm/m64

may abort a TSX transaction

PSIGND xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSIGND, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGNW