PSIGNW

PSIGNW is PSIGNB for words: each word of the destination is negated where the matching source word is negative, cleared where it is zero and kept where it is positive, eight words in an XMM register and four in an MMX one. PSIGNB’s page covers the SSSE3 history and why plain C with that three-way choice does not compile to it. Negation wraps, so -32768 stays as it is.

Zen 5’s recorded cases show two uses of the rule:

• psignw xmm4, xmm4, with one register as both operands, turned FFFFh into 0001h and left 0001h, 7FFFh and 8000h as they were: a word signed by itself is its absolute value, with the same 8000h edge as PABSW;
• psignw xmm7, xmmword ptr [mem] turned 7FFFh into 8001h and left 8000h unchanged where the source words were negative, and kept the words whose source was positive. Both cases left bits 511:128 of the register as they were (see mixing SSE and AVX).

In compiled code#

In our builds at -O2, GCC 14 and Clang 23 emit PSIGNW only for the intrinsic _mm_sign_epi16. Over fixed-size int16_t arrays with -mssse3, b[i] < 0 ? -a[i] : (b[i] == 0 ? 0 : a[i]) becomes PSUBW, PCMPEQW, PCMPGTW and a select with PAND, PANDN and POR in both, and VPBLENDVB with -mavx2, as for bytes; the plain absolute value is PABSW, never PSIGNW of a register with itself.

AMD’s latency spreadsheet for Zen 5 gives PSIGNW one macro-op with a latency of two cycles and two per cycle, on pipes FP0 and FP3, for the XMM form; the MMX form is listed with the same pipes and throughput. The XMM form’s memory operand must be aligned to 16 bytes, and VPSIGNW is the VEX form, with no EVEX encoding.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = mm1.w[i]
    b = src2.w[i]
    sb = src2.sw[i]
    if sb < 0:
        mm1.w[i] = -a
    elif b == 0:
        mm1.w[i] = 0
    else:
        mm1.w[i] = a
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

for i in range(8):
    a = xmm1.w[i]
    b = src2.w[i]
    sb = src2.sw[i]
    if sb < 0:
        xmm1.w[i] = -a
    elif b == 0:
        xmm1.w[i] = 0
    else:
        xmm1.w[i] = a
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSIGNW mm, mm/m64

mmx-mem

PSIGNW xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSIGNW mm, mm/m64

may abort a TSX transaction

PSIGNW xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSIGNW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND