PSLLD instruction (MMX, SSE2)

PSLLD shifts each doubleword of an XMM register (four) or an MMX register (two) left by one shared count, filling with zeros and setting no flag. The count follows the family’s rules, which PSLLW describes: an immediate or the low quadword of a register or of memory, never masked, so that any count above 31 clears every element. On Zen 5, the recorded pslld xmm7, 1 turned 7FFFFFFFh into FFFFFFFEh and 80000000h into 0, and pslld xmm8, xmm15 with a count of 33 cleared all four elements, where SHL would have masked the count to 1. pslld xmm12, xmmword ptr [mem] took its count, 3, from the low quadword and ignored the eight bytes above it. The XMM cases left bits 511:128 of the register as they were (see mixing SSE and AVX).

In compiled code

In our builds at -O2 for the x86-64 baseline, over uint32_t arrays:

Multiplying by constants. b[i] * 8 is PSLLD by 3 in GCC 14 and Clang 23, and b[i] * 5 is PSLLD by 2 and a PADDD of the original: until SSE4.1’s PMULLD, a product of doublewords costs two PMULUDQ and several shuffles. For b[i] << 1 Clang adds the register to itself instead.
A count per element. b[i] << c[i] has no SSE instruction. GCC keeps the loop scalar, with SHL. Clang shifts each count left by 23, into the exponent field of a single, adds 3F800000h, the bits of 1.0f, and converts the resulting 2^c back with CVTTPS2DQ, turning the shift into a multiplication (PMULLD with -march=x86-64-v2). AVX2’s VPSLLVD does it in one instruction in both.
Sign-extending a low byte in place. Clang compiles (int32_t)(x << 24) >> 24 to PSLLD and PSRAD by 24.

Intel’s optimization manual builds constants without loading them: PCMPEQD sets every bit, and PSLLD by n leaves -2^n in each doubleword (Section 6.5). Our compilers fold that away: _mm_slli_epi32 of all ones by 4 becomes MOV, MOVD and PSHUFD in GCC 14 and a load in Clang 23.

AMD’s latency spreadsheet for Zen 5 gives the form with the count in a register or memory two cycles, two per cycle, on pipes FP0 and FP1; the immediate form uses FP2 and FP3. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSLLD is the VEX and EVEX form.

Forms

Every encoding of PSLLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSLLD mm, imm8` PSLLD_MMXq_IMMb	`NP 0F 72 /6 ib`	MMX
`PSLLD xmm, imm8` PSLLD_XMMdq_IMMb	`66 0F 72 /6 ib`	SSE2
`PSLLD mm, m64` PSLLD_MMXq_MEMq	`NP 0F F2 /r`	MMX
`PSLLD mm, mm` PSLLD_MMXq_MMXq	`NP 0F F2 /r`	MMX
`PSLLD xmm, m128` PSLLD_XMMdq_MEMdq	`66 0F F2 /r`	SSE2
`PSLLD xmm, xmm` PSLLD_XMMdq_XMMdq	`66 0F F2 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.PSLLD mm, imm8 PSLLD xmm, imm8

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1. Result doublewords 3 to 0: r3, r2, r1, r0.

Element-wise, by one count: each doubleword is shifted by the count in the low 64 bits of xmm2.PSLLD mm, mm/m64 PSLLD xmm, xmm/m128

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1 and the count in xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSLLD mm, imm8

for i in range(2):
    a = mm1.d[i]
    mm1.d[i] = a << imm8 if imm8 < 32 else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSLLD xmm, imm8

for i in range(4):
    a = xmm1.d[i]
    if imm8 < 32:
        xmm1.d[i] = a << imm8
    else:
        xmm1.d[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSLLD mm, mm/m64

count = src2.q[0]
for i in range(2):
    a = mm1.d[i]
    if count < 32:
        mm1.d[i] = a << count
    else:
        mm1.d[i] = 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSLLD xmm, xmm/m128

count = src2.q[0]
for i in range(4):
    a = xmm1.d[i]
    if count < 32:
        xmm1.d[i] = a << count
    else:
        xmm1.d[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSLLD mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSLLD xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSLLD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSLLD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSLLD mm, imm8 PSLLD mm, mm/m64: mmx-mem
PSLLD xmm, imm8 PSLLD xmm, xmm: SSE_TYPE_7
PSLLD xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSLLD mm, imm8 PSLLD mm, mm/m64: may abort a TSX transaction
PSLLD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSLLD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sll_epi32` `__m128i _mm_sll_epi32(__m128i __a, __m128i __count)`	`PSLLD xmm, xmm` Legacy -msse2
`_mm_sll_pi32` `__m64 _mm_sll_pi32(__m64 __m, __m64 __count)`	`PSLLD xmm, xmm` Legacy -msse2
`_mm_slli_epi32` `__m128i _mm_slli_epi32(__m128i __a, int __count)`	`PSLLD xmm, imm8` Legacy -msse2with __count a constant
`_mm_slli_pi32` `__m64 _mm_slli_pi32(__m64 __m, int __count)`	`PSLLD xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#