PSLLDQ instruction (SSE2)

PSLLDQ shifts a whole XMM register left by a number of bytes, not bits, filling the low end with zero bytes: with an immediate of 4, byte 0 moves to byte 4 and bytes 12 to 15 fall off. Any count above 15 clears the register (Intel’s optimization manual says so too, Section 6.6.14). The count is always an immediate and there is no memory operand; for a count chosen at run time, PSHUFB with a selector vector loaded from a table does the same job.

The name invites a mix-up with PSLLQ, which shifts each quadword by bits. The intrinsics keep the difference visible: _mm_slli_si128 and its clearer alias _mm_bslli_si128 (b for bytes) compile to PSLLDQ, while _mm_slli_epi64 is PSLLQ.

Where it turns up

Prefix sums. Adding a vector to itself shifted by one element, then by two, leaves in each element the sum of all elements up to it: GCC 14 and Clang 23 at -O2 compile that with _mm_slli_si128 by 4 and 8 to two PSLLDQs and two PADDDs. Intel’s optimization manual uses the same running XOR with three shifts by 4 in its AES key expansion (Section 6.10.2).
Joining bytes. Without SSSE3’s PALIGNR, a byte rotation or a window across two registers is PSLLDQ of one, PSRLDQ of the other and POR; this is what both compilers emit for such shuffles when compiling for the SSE2 baseline.
Reductions. The mirror image, PSRLDQ, brings the high elements down so that they can be added to the low ones; GCC 14 ends its vectorized integer sums with PSRLDQ by 8 and then by 4, where Clang 23 uses PSHUFD.

For Golden Cove cores, Intel’s optimization manual lists both byte shifts among the instructions of the shuffle units, with PALIGNR, rather than with the shifts (Table 2-4). The VEX and EVEX forms, VPSLLDQ, shift each 128-bit lane separately, so no byte crosses from the low lane to the high one, and the EVEX form can also read the vector to shift from memory.

Forms

Every encoding of PSLLDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSLLDQ xmm, imm8` PSLLDQ_XMMdq_IMMb	`66 0F 73 /7 ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Byte shift: the bytes move up by imm8 places within each 128-bit lane, and zeros come in.

Example: imm8 = 3.

With imm8 = 3, result bytes 15 to 0: a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0, 0, 0, 0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(16):
    if i >= imm8:
        xmm1.b[i] = src1.b[i - imm8]
    else:
        xmm1.b[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSLLDQ xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_7

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSLLDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_bslli_si128` `__m128i _mm_bslli_si128(__m128i a, const int imm)`	`PSLLDQ xmm, imm8` Legacy -msse2
`_mm_slli_si128` `__m128i _mm_slli_si128(__m128i a, const int imm)`	`PSLLDQ xmm, imm8` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Where it turns up#