PSLLQ instruction (MMX, SSE2)

PSLLQ shifts each quadword of an XMM register, or the one quadword of an MMX register, left by the same count, filling with zeros. The count is an immediate or the low quadword of another register or of memory, read whole and not masked, as PSLLW describes for the whole family: any count above 63 clears every element. On Zen 5, the recorded psllq mm1, [mem] with a count of 8000000000000000h cleared the register rather than shifting by 0, and the XMM cases with a count in a register or in memory ignored whatever the high quadword of the count held. The legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX).

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

Shifts of 64-bit elements. a[i] = b[i] << 3 over uint64_t is PSLLQ by 3; with a count n in a variable, both move it in with MOVD and shift by register.
A count per element. b[i] << c[i] has no SSE instruction. GCC keeps the loop scalar, with SAL; Clang shifts the whole vector twice, once by each element’s count, the second brought down with PSHUFD, and keeps one quadword of each result with MOVSD, or PBLENDW with -march=x86-64-v2. AVX2’s VPSLLVQ does it in one instruction.
64-bit products. SSE has no quadword multiply, so Clang computes b[i] * c[i] over uint64_t from 32-bit pieces: two PSRLQ by 32 bring the high halves down, three PMULUDQ form the partial products, and PSLLQ by 32 moves the sum of the cross products up before the final PADDQ. GCC keeps the loop scalar, with IMUL. Intel’s optimization manual shows the same sequence in AVX2 against the one instruction of AVX-512, VPMULLQ (Section 17.13.1).

PSLLQ shifts each quadword separately, and bits do not cross from one to the next; a shift of the whole 128-bit register by bits takes shifts of both quadwords, a byte shift with PSLLDQ to carry bits across the middle, and an OR. AMD’s latency spreadsheet for Zen 5 gives the form with the count in a register two cycles, two per cycle, on pipes FP0 and FP1; the immediate form uses FP2 and FP3. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSLLQ is the VEX and EVEX form.

Forms

Every encoding of PSLLQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSLLQ mm, imm8` PSLLQ_MMXq_IMMb	`NP 0F 73 /6 ib`	MMX
`PSLLQ xmm, imm8` PSLLQ_XMMdq_IMMb	`66 0F 73 /6 ib`	SSE2
`PSLLQ mm, m64` PSLLQ_MMXq_MEMq	`NP 0F F3 /r`	MMX
`PSLLQ mm, mm` PSLLQ_MMXq_MMXq	`NP 0F F3 /r`	MMX
`PSLLQ xmm, m128` PSLLQ_XMMdq_MEMdq	`66 0F F3 /r`	SSE2
`PSLLQ xmm, xmm` PSLLQ_XMMdq_XMMdq	`66 0F F3 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.PSLLQ mm, imm8 PSLLQ xmm, imm8

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1. Result quadwords 1 to 0: r1, r0.

Element-wise, by one count: each quadword is shifted by the count in the low 64 bits of xmm2.PSLLQ mm, mm/m64 PSLLQ xmm, xmm/m128

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and the count in xmm2. Result quadwords 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSLLQ mm, imm8

i = 0
a = mm1.q[i]
mm1.q[i] = a << imm8 if imm8 < 64 else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSLLQ xmm, imm8

for i in range(2):
    a = xmm1.q[i]
    if imm8 < 64:
        xmm1.q[i] = a << imm8
    else:
        xmm1.q[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSLLQ mm, mm/m64

count = src2.q[0]
i = 0
a = mm1.q[i]
mm1.q[i] = a << count if count < 64 else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSLLQ xmm, xmm/m128

count = src2.q[0]
for i in range(2):
    a = xmm1.q[i]
    if count < 64:
        xmm1.q[i] = a << count
    else:
        xmm1.q[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSLLQ mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSLLQ xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSLLQ mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSLLQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSLLQ mm, imm8 PSLLQ mm, mm/m64: mmx-mem
PSLLQ xmm, imm8 PSLLQ xmm, xmm: SSE_TYPE_7
PSLLQ xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSLLQ mm, imm8 PSLLQ mm, mm/m64: may abort a TSX transaction
PSLLQ xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSLLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sll_epi64` `__m128i _mm_sll_epi64(__m128i __a, __m128i __count)`	`PSLLQ xmm, xmm` Legacy -msse2
`_mm_sll_si64` `__m64 _mm_sll_si64(__m64 __m, __m64 __count)`	`PSLLQ xmm, xmm` Legacy -msse2
`_mm_slli_epi64` `__m128i _mm_slli_epi64(__m128i __a, int __count)`	`PSLLQ xmm, imm8` Legacy -msse2with __count a constant
`_mm_slli_si64` `__m64 _mm_slli_si64(__m64 __m, int __count)`	`PSLLQ xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#