PSLLW instruction (MMX, SSE2)

PSLLW shifts every word of an MMX or XMM register left by the same count, filling with zeros. The count comes from an immediate or from the low quadword of another register or of memory, and it is not masked as the count of SHL is: any count above 15 clears every word, and the whole 64-bit value counts, so a count of 100000000h clears the register too rather than acting as 0. The intrinsics are _mm_slli_epi16 for an immediate and _mm_sll_epi16 for a count in a vector, whose low 64 bits only are read.

In compiled code

GCC 14 and Clang 23 at -O2 vectorize a[i] << 3 over uint16_t arrays to PSLLW by 3. With a count held in a variable they do not use it: C shifts the words as int, and both compilers widen them to doublewords and shift with PSLLD, although truncated to 16 bits the result is the same. The intrinsic _mm_sll_epi16 with the count moved in by MOVD gets PSLLW by register. Both fold constant counts above 15 away, compiling _mm_slli_epi16(v, 20) to a zeroed register. For a shift by 1, Clang prefers PADDW of the register with itself; GCC keeps PSLLW.

There is no byte shift. For uint8_t elements shifted by 3, Clang shifts words with PSLLW and clears the bits that crossed into the next byte with PAND and F8h in every byte; GCC adds each vector to itself three times with PADDB. Swapping the bytes of each word is PSLLW by 8, PSRLW by 8 and POR in both compilers, until SSSE3 offers PSHUFB.

For Golden Cove, Intel’s optimization manual places vector shifts with an immediate count on two execution units but those with the count in an XMM register on one, shared with PSADBW and PCLMULQDQ (Table 2-4).

Wider forms

VPSLLW, the VEX and EVEX form, writes a separate destination and shifts every word of a YMM or ZMM register by the one count, which still comes from an immediate or the low quadword of an XMM register or of memory. Shifting each word by its own count needs AVX512BW’s VPSLLVW; AVX2 has such shifts only for doublewords and quadwords (VPSLLVD). PSLLD and PSLLQ are the same instruction for larger elements.

Forms

Every encoding of PSLLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSLLW mm, imm8` PSLLW_MMXq_IMMb	`NP 0F 71 /6 ib`	MMX
`PSLLW xmm, imm8` PSLLW_XMMdq_IMMb	`66 0F 71 /6 ib`	SSE2
`PSLLW mm, m64` PSLLW_MMXq_MEMq	`NP 0F F1 /r`	MMX
`PSLLW mm, mm` PSLLW_MMXq_MMXq	`NP 0F F1 /r`	MMX
`PSLLW xmm, m128` PSLLW_XMMdq_MEMdq	`66 0F F1 /r`	SSE2
`PSLLW xmm, xmm` PSLLW_XMMdq_XMMdq	`66 0F F1 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.PSLLW mm, imm8 PSLLW xmm, imm8

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Element-wise, by one count: each word is shifted by the count in the low 64 bits of xmm2.PSLLW mm, mm/m64 PSLLW xmm, xmm/m128

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and the count in xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSLLW mm, imm8

for i in range(4):
    a = mm1.w[i]
    mm1.w[i] = a << imm8 if imm8 < 16 else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSLLW xmm, imm8

for i in range(8):
    a = xmm1.w[i]
    if imm8 < 16:
        xmm1.w[i] = a << imm8
    else:
        xmm1.w[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSLLW mm, mm/m64

count = src2.q[0]
for i in range(4):
    a = mm1.w[i]
    if count < 16:
        mm1.w[i] = a << count
    else:
        mm1.w[i] = 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSLLW xmm, xmm/m128

count = src2.q[0]
for i in range(8):
    a = xmm1.w[i]
    if count < 16:
        xmm1.w[i] = a << count
    else:
        xmm1.w[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSLLW mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSLLW xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSLLW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSLLW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSLLW mm, imm8 PSLLW mm, mm/m64: mmx-mem
PSLLW xmm, imm8 PSLLW xmm, xmm: SSE_TYPE_7
PSLLW xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSLLW mm, imm8 PSLLW mm, mm/m64: may abort a TSX transaction
PSLLW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSLLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sll_epi16` `__m128i _mm_sll_epi16(__m128i __a, __m128i __count)`	`PSLLW xmm, xmm` Legacy -msse2
`_mm_sll_pi16` `__m64 _mm_sll_pi16(__m64 __m, __m64 __count)`	`PSLLW xmm, xmm` Legacy -msse2
`_mm_slli_epi16` `__m128i _mm_slli_epi16(__m128i __a, int __count)`	`PSLLW xmm, imm8` Legacy -msse2with __count a constant
`_mm_slli_pi16` `__m64 _mm_slli_pi16(__m64 __m, int __count)`	`PSLLW xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#

Wider forms#