PSMASH instruction (SEV-SNP)

Forms

Every encoding of PSMASH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSMASH RAX` 64-bit mode only PSMASH_RAX	`F3 0F 01 FF`	SNP

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not msr[SYSCFG] >> 24 & 1:
    fault(UD)                    # SEV-SNP off (SYSCFG.SNPEn)
if CPL > 0:
    fault(GP, 0)
spa = addr.read() & ~0x1FFFFF    # RAX: a 2-MB page
if asid != 0:
    eax = 2                      # FAIL_PERMISSION: the hypervisor
                                 # alone, at ASID 0
elif not in_rmp(spa):
    eax = 1                      # FAIL_INPUT: no RMP entry
else:
    r = rmp(spa)
    if r >> 80 & 1 or not r >> 64 & 1:
        eax = 7                  # FAIL_BADADDR: immutable, or free
    elif not r >> 72 & 1:
        eax = 7                  # FAIL_BADADDR: no 2-MB page
    else:
        r = r & ~(1 << 72)       # 512 pages of 4 KB, the same but
        for i in range(512):     # for their guest addresses
            a = spa + 4096 * i
            set_rmp(a, r + 4096 * i)
        eax = 0                  # SUCCESS
of = zf = af = pf = sf = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no SEV-SNP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSMASH RAX` 64-bit mode only
`RAX`	explicit	read, write
`RFLAGS`	implicit	write

Flags

M modified; blank: not affected. How to read.

OF	SF	ZF	AF	PF
All forms
M	M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: privileged: CPL 0 only

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SNP` SEV-SNP	SNP `CPUID.8000001FH:EAX[4]` SNP	Zen 3, Zen 4, Zen 5, Zen 6 Note: Only the EPYC server processors have SEV-SNP: AMD's references for the Ryzen processors of Zen 3, Zen 4 and Zen 5 leave CPUID_Fn8000001F_EAX[SNP] (bit 4) clear.

PSMASH