PSRAD instruction (MMX, SSE2)

PSRAD shifts every doubleword of an MMX or XMM register right by the same count, copying each element’s sign bit into the vacated bits, as SAR does. The count comes from an immediate or from the low quadword of another register or of memory, unmasked: any count of 32 or more leaves each element all sign, 0 for a non-negative one and FFFFFFFFh for a negative one, where the logical PSRLD clears everything. A shift by 31 is therefore the vector way to turn each element into a mask of its sign.

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

Sign masks. abs() over int32_t elements becomes PSRAD by 31, PXOR of the mask into the value and PSUBD of the mask, until SSSE3’s PABSD does it in one instruction.
Signed division by a power of two. Like SAR, PSRAD rounds toward minus infinity, so x / 4 needs 3 added to negative elements first. Clang computes that bias with PSRAD by 31 and PSRLD by 30, adds it and shifts by 2; GCC makes the mask with PCMPGTD against zero and ANDs it with 3.
Sign extension. To widen int16_t elements to int32_t, Clang interleaves the data with itself by PUNPCKLWD, which puts each word in the upper half of a doubleword, and shifts arithmetically by 16, the method Intel’s optimization manual gives for signed unpacking (Section 6.4.2). SSE4.1’s PMOVSXWD replaces both.
A count in a variable, a[i] >>= n, is a MOVD of n into an XMM register and PSRAD by register.

No quadword form

SSE and AVX2 have arithmetic shifts for words (PSRAW) and doublewords only. For int64_t elements shifted by 5, both compilers combine PSRAD of the high halves with PSRLQ of the whole quadwords and shuffle the two together. AVX-512 added the quadword shift, VPSRAQ, and AVX2 the per-element counts of VPSRAVD, which also fill with the sign when a count exceeds 31. VPSRAD is the VEX and EVEX form of PSRAD.

Forms

Every encoding of PSRAD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSRAD mm, imm8` PSRAD_MMXq_IMMb	`NP 0F 72 /4 ib`	MMX
`PSRAD xmm, imm8` PSRAD_XMMdq_IMMb	`66 0F 72 /4 ib`	SSE2
`PSRAD mm, m64` PSRAD_MMXq_MEMq	`NP 0F E2 /r`	MMX
`PSRAD mm, mm` PSRAD_MMXq_MMXq	`NP 0F E2 /r`	MMX
`PSRAD xmm, m128` PSRAD_XMMdq_MEMdq	`66 0F E2 /r`	SSE2
`PSRAD xmm, xmm` PSRAD_XMMdq_XMMdq	`66 0F E2 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.PSRAD mm, imm8 PSRAD xmm, imm8

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1. Result doublewords 3 to 0: r3, r2, r1, r0.

Element-wise, by one count: each doubleword is shifted by the count in the low 64 bits of xmm2.PSRAD mm, mm/m64 PSRAD xmm, xmm/m128

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1 and the count in xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSRAD mm, imm8

for i in range(2):
    mm1.d[i] = mm1.sd[i] >> imm8
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRAD xmm, imm8

for i in range(4):
    xmm1.d[i] = xmm1.sd[i] >> imm8
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRAD mm, mm/m64

count = src2.q[0]
for i in range(2):
    mm1.d[i] = mm1.sd[i] >> count
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSRAD xmm, xmm/m128

count = src2.q[0]
for i in range(4):
    xmm1.d[i] = xmm1.sd[i] >> count
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSRAD mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSRAD xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSRAD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSRAD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSRAD mm, imm8 PSRAD mm, mm/m64: mmx-mem
PSRAD xmm, imm8 PSRAD xmm, xmm: SSE_TYPE_7
PSRAD xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSRAD mm, imm8 PSRAD mm, mm/m64: may abort a TSX transaction
PSRAD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSRAD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sra_epi32` `__m128i _mm_sra_epi32(__m128i __a, __m128i __count)`	`PSRAD xmm, xmm` Legacy -msse2
`_mm_sra_pi32` `__m64 _mm_sra_pi32(__m64 __m, __m64 __count)`	`PSRAD xmm, xmm` Legacy -msse2
`_mm_srai_epi32` `__m128i _mm_srai_epi32(__m128i __a, int __count)`	`PSRAD xmm, imm8` Legacy -msse2with __count a constant
`_mm_srai_pi32` `__m64 _mm_srai_pi32(__m64 __m, int __count)`	`PSRAD xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#

No quadword form#