PSRAW instruction (MMX, SSE2)

PSRAW shifts every word of an XMM or MMX register right by the same count, copying each word’s sign bit into the vacated bits. Like PSRAD, whose page covers the shared behaviour, it reads its count from an immediate or from the whole low quadword of a register or of memory, and a count of 16 or more leaves each word all sign, 0000h or FFFFh. On Zen 5, the recorded psraw xmm7, 1 turned 8000h into C000h and 7FFFh into 3FFFh, and psraw xmm4, xmm4, whose low quadword gave a count of 15, reduced every word to its sign. The legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX).

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

Division by a power of two. b[i] >> 3 over int16_t is PSRAW by 3, which rounds toward minus infinity. For b[i] / 4, rounding toward zero needs 3 added to negative elements first: Clang makes it with PSRAW by 15 and PSRLW by 14, GCC with PCMPGTW against zero and a PAND.
Signed bytes. No byte shift exists, so b[i] >> 3 over int8_t shifts words, GCC with PSRAW and Clang with PSRLW, keeps the five valid bits of each byte with a PAND of 1Fh, and extends their sign with a PXOR and a PSUBB of 10h.
Sign extension. To widen int8_t to int16_t, Clang puts each byte in the high half of a word with PUNPCKLBW of a register with itself and shifts by 8; GCC builds the high bytes with PCMPGTB against zero instead. SSE4.1’s PMOVSXBW replaces both.
Signed averages. For (b[i] + c[i] + 1) >> 1 over int16_t, Clang computes (b | c) - ((b ^ c) >> 1) with PSRAW, where the unsigned average is PAVGW.

AMD’s latency spreadsheet for Zen 5 gives the form with the count in a register two cycles, two per cycle. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSRAW is the VEX and EVEX form, and AVX512BW’s VPSRAVW takes a count per word.

Forms

Every encoding of PSRAW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSRAW mm, imm8` PSRAW_MMXq_IMMb	`NP 0F 71 /4 ib`	MMX
`PSRAW xmm, imm8` PSRAW_XMMdq_IMMb	`66 0F 71 /4 ib`	SSE2
`PSRAW mm, m64` PSRAW_MMXq_MEMq	`NP 0F E1 /r`	MMX
`PSRAW mm, mm` PSRAW_MMXq_MMXq	`NP 0F E1 /r`	MMX
`PSRAW xmm, m128` PSRAW_XMMdq_MEMdq	`66 0F E1 /r`	SSE2
`PSRAW xmm, xmm` PSRAW_XMMdq_XMMdq	`66 0F E1 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.PSRAW mm, imm8 PSRAW xmm, imm8

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Element-wise, by one count: each word is shifted by the count in the low 64 bits of xmm2.PSRAW mm, mm/m64 PSRAW xmm, xmm/m128

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and the count in xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSRAW mm, imm8

for i in range(4):
    mm1.w[i] = mm1.sw[i] >> imm8
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRAW xmm, imm8

for i in range(8):
    xmm1.w[i] = xmm1.sw[i] >> imm8
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRAW mm, mm/m64

count = src2.q[0]
for i in range(4):
    mm1.w[i] = mm1.sw[i] >> count
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSRAW xmm, xmm/m128

count = src2.q[0]
for i in range(8):
    xmm1.w[i] = xmm1.sw[i] >> count
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSRAW mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSRAW xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSRAW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSRAW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSRAW mm, imm8 PSRAW mm, mm/m64: mmx-mem
PSRAW xmm, imm8 PSRAW xmm, xmm: SSE_TYPE_7
PSRAW xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSRAW mm, imm8 PSRAW mm, mm/m64: may abort a TSX transaction
PSRAW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSRAW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sra_epi16` `__m128i _mm_sra_epi16(__m128i __a, __m128i __count)`	`PSRAW xmm, xmm` Legacy -msse2
`_mm_sra_pi16` `__m64 _mm_sra_pi16(__m64 __m, __m64 __count)`	`PSRAW xmm, xmm` Legacy -msse2
`_mm_srai_epi16` `__m128i _mm_srai_epi16(__m128i __a, int __count)`	`PSRAW xmm, imm8` Legacy -msse2with __count a constant
`_mm_srai_pi16` `__m64 _mm_srai_pi16(__m64 __m, int __count)`	`PSRAW xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#