PSRLD instruction (MMX, SSE2)

PSRLD shifts each doubleword of an XMM register (four) or an MMX register (two) right by one shared count, filling with zeros, where PSRAD copies the sign. The count follows the family’s rules, which PSLLW describes: anything above 31 clears every element. The cases recorded on Zen 5 show the edges: psrld mm7, 3 turned 80000000h into 10000000h, with no sign copied; psrld xmm7, 0x20 cleared all four elements; and psrld xmm8, xmm15, whose count quadword was 8000000000000000h, cleared XMM8 as well, although its low doubleword alone would have meant a shift by 0. The XMM forms left bits 511:128 as they were (see mixing SSE and AVX).

In compiled code

In our builds at -O2 for the x86-64 baseline, over uint32_t arrays:

Unsigned division. b[i] / 8 is PSRLD by 3. b[i] / 7 takes the high halves of products by 24924925h with PMULUDQ, then a PSUBD, PSRLD by 1, PADDD and PSRLD by 2, in GCC 14 and Clang 23 alike.
Unsigned to float. SSE2 converts only signed doublewords. For (float)b[i], GCC 14 converts the high halves, brought down by PSRLD 16, with CVTDQ2PS, multiplies them by 65536.0 and adds the converted low halves; Clang 23 ORs the high halves, again shifted down by 16, into the float 2^39 and the low ones into 2^23, then subtracts 2^39 + 2^23 and adds.
Narrowing. To store b[i] >> 16 as uint16_t, Clang shifts with PSRAD instead, so that PACKSSDW keeps every bit, and switches to PSRLD and PACKUSDW with -march=x86-64-v2.
A count per element. For b[i] >> c[i] GCC keeps SHR; Clang shifts the whole vector once by each of the four counts and blends the results, until AVX2’s VPSRLVD.

Intel’s optimization manual converts RGBA pixels to BGRA with PSRLD and PSLLD by 16 and masks, and shows SSSE3’s PSHUFB replacing those six SSE2 instructions (Section 6.6.4).

AMD’s latency spreadsheet for Zen 5 gives the register and memory count forms two cycles, two per cycle, on FP0 and FP1, and the immediate form FP2 and FP3. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSRLD is the VEX and EVEX form.

Forms

Every encoding of PSRLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSRLD mm, imm8` PSRLD_MMXq_IMMb	`NP 0F 72 /2 ib`	MMX
`PSRLD xmm, imm8` PSRLD_XMMdq_IMMb	`66 0F 72 /2 ib`	SSE2
`PSRLD mm, m64` PSRLD_MMXq_MEMq	`NP 0F D2 /r`	MMX
`PSRLD mm, mm` PSRLD_MMXq_MMXq	`NP 0F D2 /r`	MMX
`PSRLD xmm, m128` PSRLD_XMMdq_MEMdq	`66 0F D2 /r`	SSE2
`PSRLD xmm, xmm` PSRLD_XMMdq_XMMdq	`66 0F D2 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.PSRLD mm, imm8 PSRLD xmm, imm8

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1. Result doublewords 3 to 0: r3, r2, r1, r0.

Element-wise, by one count: each doubleword is shifted by the count in the low 64 bits of xmm2.PSRLD mm, mm/m64 PSRLD xmm, xmm/m128

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1 and the count in xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSRLD mm, imm8

for i in range(2):
    mm1.d[i] = mm1.d[i] >> imm8
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRLD xmm, imm8

for i in range(4):
    xmm1.d[i] = xmm1.d[i] >> imm8
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRLD mm, mm/m64

count = src2.q[0]
for i in range(2):
    mm1.d[i] = mm1.d[i] >> count
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSRLD xmm, xmm/m128

count = src2.q[0]
for i in range(4):
    xmm1.d[i] = xmm1.d[i] >> count
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSRLD mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSRLD xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSRLD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSRLD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSRLD mm, imm8 PSRLD mm, mm/m64: mmx-mem
PSRLD xmm, imm8 PSRLD xmm, xmm: SSE_TYPE_7
PSRLD xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSRLD mm, imm8 PSRLD mm, mm/m64: may abort a TSX transaction
PSRLD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSRLD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_srl_epi32` `__m128i _mm_srl_epi32(__m128i __a, __m128i __count)`	`PSRLD xmm, xmm` Legacy -msse2
`_mm_srl_pi32` `__m64 _mm_srl_pi32(__m64 __m, __m64 __count)`	`PSRLD xmm, xmm` Legacy -msse2
`_mm_srli_epi32` `__m128i _mm_srli_epi32(__m128i __a, int __count)`	`PSRLD xmm, imm8` Legacy -msse2with __count a constant
`_mm_srli_pi32` `__m64 _mm_srli_pi32(__m64 __m, int __count)`	`PSRLD xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#