PSRLDQ instruction (SSE2)

PSRLDQ shifts a whole XMM register right by a number of bytes, filling the high end with zero bytes: with an immediate of 4, bytes 4 to 15 move down to 0 to 11 and bytes 12 to 15 become zero. The count is always an immediate, and any count above 15 clears the register: on Zen 5, the recorded psrldq xmm0, 0x10 set all 16 bytes to zero and, as legacy SSE instructions do, left bits 255:128 as they were (see mixing SSE and AVX). There is no MMX form and no memory operand. PSLLDQ, its mirror image, describes the pair and the mix-up with PSRLQ, which shifts each quadword by bits.

Where it turns up

Bringing the high elements down is the classic way to finish a reduction, adding or comparing a register with its upper half, then with its upper quarter. In our builds at -O2 for the SSE2 baseline:

Sums. GCC 14 ends s += b[i] over int with PSRLDQ by 8 and by 4, each followed by a PADDD; Clang 23 uses PSHUFD for the same steps. Intel’s optimization manual adds its partial sums the same way (Section 3.6.1.1, Example 3-32).
Extremes. For the largest byte of a uint8_t array, GCC halves the register four times, by 8, 4, 2 and 1 bytes, with a PMAXUB after each, and the smallest int16_t takes three steps with PMINSW.
Widening with SSE4.1. With -march=x86-64-v2, GCC sign-extends the high half of a register by shifting it down with PSRLDQ by 8 before PMOVSXBW, which reads only the low half.

_mm_srli_si128 and _mm_bsrli_si128 compile to it. For a count of 16, GCC 14 still emits PSRLDQ by 16 while Clang 23 zeroes the register with XORPS.

Intel’s manual lists PSRLDQ with the shuffles rather than the shifts in Golden Cove’s execution units (Table 2-4), and AMD’s latency spreadsheet for Zen 5 puts it on pipes FP1 and FP2, two per cycle, where the bit shifts by an immediate use FP2 and FP3. The VEX and EVEX forms, VPSRLDQ, shift each 128-bit lane on its own.

Forms

Every encoding of PSRLDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSRLDQ xmm, imm8` PSRLDQ_XMMdq_IMMb	`66 0F 73 /3 ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Byte shift: the bytes move down by imm8 places within each 128-bit lane, and zeros come in.

Example: imm8 = 3.

With imm8 = 3, result bytes 15 to 0: 0, 0, 0, a15, a14, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(16):
    if i + imm8 < 16:
        xmm1.b[i] = src1.b[i + imm8]
    else:
        xmm1.b[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSRLDQ xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_7

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSRLDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_bsrli_si128` `__m128i _mm_bsrli_si128(__m128i a, const int imm)`	`PSRLDQ xmm, imm8` Legacy -msse2
`_mm_srli_si128` `__m128i _mm_srli_si128(__m128i a, const int imm)`	`PSRLDQ xmm, imm8` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Where it turns up#