PSRLQ instruction (MMX, SSE2)

PSRLQ shifts each quadword of an XMM register, or the one quadword of an MMX register, right by the same count, filling with zeros. The count is an immediate or the low quadword of another register or of memory, not masked as the count of SHR is: anything above 63 clears the element, as PSLLW explains for the family. On Zen 5, the recorded psrlq xmm12, 3 turned 8000000000000000h into 1000000000000000h, with no sign copied, while psrlq xmm12, xmm6 with a count of 65 cleared both quadwords, where SHR would have shifted by 1, and psrlq mm0, 0xff cleared MM0. The legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX).

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

Shifts of 64-bit elements. b[i] >> 3 over uint64_t is PSRLQ by 3, and a count in a variable is moved in with MOVD.
High halves. PSRLQ by 32 brings the odd doublewords into even places: Clang does so before PMULUDQ, which reads only those, when it multiplies quadwords (see PSLLQ). For a[i] = b[i] >> 32 into uint32_t, GCC shifts and gathers with SHUFPS, while Clang picks the odd doublewords with SHUFPS alone.
Signed quadwords. There is no arithmetic quadword shift before AVX-512’s VPSRAQ. For int64_t shifted by 5, both shift whole quadwords with PSRLQ, the high doublewords with PSRAD, and combine the two with shuffles, or with one PBLENDW with -march=x86-64-v2.
Conversions. Clang converts uint64_t to double without a branch: PSRLQ by 32 and an OR place each high half in the significand of a large constant, a PAND and an OR the low half in another, and a subtraction and an addition remove the constants. GCC converts one element at a time with CVTSI2SD, halving values with the top bit set.

AMD’s latency spreadsheet for Zen 5 gives the form with the count in a register two cycles, two per cycle, on pipes FP0 and FP1; the immediate form uses FP2 and FP3. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSRLQ is the VEX and EVEX form, and AVX2’s VPSRLVQ takes a count per element.

Forms

Every encoding of PSRLQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSRLQ mm, imm8` PSRLQ_MMXq_IMMb	`NP 0F 73 /2 ib`	MMX
`PSRLQ xmm, imm8` PSRLQ_XMMdq_IMMb	`66 0F 73 /2 ib`	SSE2
`PSRLQ mm, m64` PSRLQ_MMXq_MEMq	`NP 0F D3 /r`	MMX
`PSRLQ mm, mm` PSRLQ_MMXq_MMXq	`NP 0F D3 /r`	MMX
`PSRLQ xmm, m128` PSRLQ_XMMdq_MEMdq	`66 0F D3 /r`	SSE2
`PSRLQ xmm, xmm` PSRLQ_XMMdq_XMMdq	`66 0F D3 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.PSRLQ mm, imm8 PSRLQ xmm, imm8

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1. Result quadwords 1 to 0: r1, r0.

Element-wise, by one count: each quadword is shifted by the count in the low 64 bits of xmm2.PSRLQ mm, mm/m64 PSRLQ xmm, xmm/m128

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and the count in xmm2. Result quadwords 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSRLQ mm, imm8

i = 0
mm1.q[i] = mm1.q[i] >> imm8
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRLQ xmm, imm8

for i in range(2):
    xmm1.q[i] = xmm1.q[i] >> imm8
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRLQ mm, mm/m64

count = src2.q[0]
i = 0
mm1.q[i] = mm1.q[i] >> count
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSRLQ xmm, xmm/m128

count = src2.q[0]
for i in range(2):
    xmm1.q[i] = xmm1.q[i] >> count
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSRLQ mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSRLQ xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSRLQ mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSRLQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSRLQ mm, imm8 PSRLQ mm, mm/m64: mmx-mem
PSRLQ xmm, imm8 PSRLQ xmm, xmm: SSE_TYPE_7
PSRLQ xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSRLQ mm, imm8 PSRLQ mm, mm/m64: may abort a TSX transaction
PSRLQ xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSRLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_srl_epi64` `__m128i _mm_srl_epi64(__m128i __a, __m128i __count)`	`PSRLQ xmm, xmm` Legacy -msse2
`_mm_srl_si64` `__m64 _mm_srl_si64(__m64 __m, __m64 __count)`	`PSRLQ xmm, xmm` Legacy -msse2
`_mm_srli_epi64` `__m128i _mm_srli_epi64(__m128i __a, int __count)`	`PSRLQ xmm, imm8` Legacy -msse2with __count a constant
`_mm_srli_si64` `__m64 _mm_srli_si64(__m64 __m, int __count)`	`PSRLQ xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#