PSRLW instruction (MMX, SSE2)

PSRLW shifts every word of an MMX or XMM register right by the same count, filling with zeros. PSLLW describes the family: the count from an immediate or from the low quadword of a register or of memory, never masked, so that anything above 15 clears every word. The cases recorded on Zen 5 show both sides of that: psrlw mm7, qword ptr [mem] with a count of 15 turned 8000h and FFFFh into 0001h and 7FFFh into 0000h, while psrlw xmm0, xmmword ptr [mem] read the count 100000001h from the low quadword of its 16-byte operand and cleared every word, where SHR would have shifted by one bit. psrlw mm6, mm5 by 3 turned 8000h into 1000h, with no sign copied as PSRAW would.

Bytes through words

SSE has no byte shift, and the logical word shift stands in for one. In our builds at -O2 for the x86-64 baseline, over arrays of uint8_t:

b[i] >> 3 is PSRLW by 3 and a PAND with 1Fh in every byte, which clears the bits that came down from the byte above. The high nibble, for example to index a 16-entry table with PSHUFB, is PSRLW by 4 and a PAND with 0Fh.
The high bytes of uint16_t values, w[i] >> 8 stored as bytes, are PSRLW by 8 and PACKUSWB, which cannot saturate since every word is now below 100h; GCC 14 still ANDs with 00FFh first.

For uint16_t arrays, w[i] >> 3 is PSRLW by 3 in GCC 14 and Clang 23. With the count in a variable they shift doublewords instead, as for PSLLW, since C promotes the words to int. PSRLW by 15 also brings the sign bit of each word down to bit 0, which Clang uses to round signed division by a constant toward zero (see PMULHW).

AMD’s latency spreadsheet for Zen 5 gives the form with the count in a register two cycles on pipes FP0 and FP1, and puts the immediate form on FP2 and FP3. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes; the legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX). VPSRLW is the VEX and EVEX form, and AVX512BW’s VPSRLVW takes a count per element.

Forms

Every encoding of PSRLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSRLW mm, imm8` PSRLW_MMXq_IMMb	`NP 0F 71 /2 ib`	MMX
`PSRLW xmm, imm8` PSRLW_XMMdq_IMMb	`66 0F 71 /2 ib`	SSE2
`PSRLW mm, m64` PSRLW_MMXq_MEMq	`NP 0F D1 /r`	MMX
`PSRLW mm, mm` PSRLW_MMXq_MMXq	`NP 0F D1 /r`	MMX
`PSRLW xmm, m128` PSRLW_XMMdq_MEMdq	`66 0F D1 /r`	SSE2
`PSRLW xmm, xmm` PSRLW_XMMdq_XMMdq	`66 0F D1 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.PSRLW mm, imm8 PSRLW xmm, imm8

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Element-wise, by one count: each word is shifted by the count in the low 64 bits of xmm2.PSRLW mm, mm/m64 PSRLW xmm, xmm/m128

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and the count in xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSRLW mm, imm8

for i in range(4):
    mm1.w[i] = mm1.w[i] >> imm8
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRLW xmm, imm8

for i in range(8):
    xmm1.w[i] = xmm1.w[i] >> imm8
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

PSRLW mm, mm/m64

count = src2.q[0]
for i in range(4):
    mm1.w[i] = mm1.w[i] >> count
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSRLW xmm, xmm/m128

count = src2.q[0]
for i in range(8):
    xmm1.w[i] = xmm1.w[i] >> count
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSRLW mm, imm8`
`mm`	explicit	read, write
`imm8`	explicit	read
`PSRLW xmm, imm8`
`xmm`	explicit	read, write
`imm8`	explicit	read
`PSRLW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSRLW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSRLW mm, imm8 PSRLW mm, mm/m64: mmx-mem
PSRLW xmm, imm8 PSRLW xmm, xmm: SSE_TYPE_7
PSRLW xmm, m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSRLW mm, imm8 PSRLW mm, mm/m64: may abort a TSX transaction
PSRLW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSRLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_srl_epi16` `__m128i _mm_srl_epi16(__m128i __a, __m128i __count)`	`PSRLW xmm, xmm` Legacy -msse2
`_mm_srl_pi16` `__m64 _mm_srl_pi16(__m64 __m, __m64 __count)`	`PSRLW xmm, xmm` Legacy -msse2
`_mm_srli_epi16` `__m128i _mm_srli_epi16(__m128i __a, int __count)`	`PSRLW xmm, imm8` Legacy -msse2with __count a constant
`_mm_srli_pi16` `__m64 _mm_srli_pi16(__m64 __m, int __count)`	`PSRLW xmm, imm8` Legacy -msse2with __count a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Bytes through words#