PSUBB instruction (MMX, SSE2)

PSUBB subtracts the bytes of its second operand from those of its first and keeps the low eight bits of each difference, so the result wraps around, the same for signed and unsigned bytes, and no flag records a borrow: 16 bytes in an XMM register, 8 in an MMX register. On Zen 5, the recorded psubb xmm8, xmm15 turned 80h minus 01h into 7Fh (-128 minus 1 wrapping to 127), 7Fh minus FFh into 80h and 00h minus 01h into FFh, and left bits 255:128 of the register as they were (see mixing SSE and AVX). The subtractions that clamp instead of wrapping are PSUBSB for signed and PSUBUSB for unsigned bytes. PADDD covers what the family’s legacy forms share.

Bytes in compiled code

In our builds at -O2 for the x86-64 baseline, over arrays of 1,024 bytes:

Differences. a[i] = b[i] - c[i] over uint8_t is one PSUBB per 16 bytes with the second operand from memory, in GCC 14 and Clang 23.
Negation. There is no negate: -b[i] is PSUBB from a register zeroed with PXOR.
Constants. b[i] - 'a' is not a subtraction at all: both add 9Fh, the negated constant, with PADDB.
Bit counts. Clang vectorizes __builtin_popcount of each byte with the classic first step, x - ((x >> 1) & 55h): there is no byte shift, so it shifts words with PSRLW, lets the PAND drop the bits that crossed from the neighbouring byte, and subtracts with PSUBB, then sums pairs and nibbles with PADDB. GCC calls the library’s __popcountdi2 for every byte. With -march=x86-64-v2, Clang looks the count of each nibble up with PSHUFB instead, and GCC uses the scalar POPCNT.

A register minus itself is zero: the recorded psubb mm3, mm3 cleared MM3 whatever it held. Intel’s optimization manual lists PSUBB of an XMM register with itself among the idioms that break the dependency on the old value (Section 3.5.1.7); which cores take the legacy form so, the guide’s zeroing idioms section covers. Compilers zero with PXOR.

AMD’s latency spreadsheet for Zen 5 gives PSUBB one cycle, four per cycle. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSUBB is the VEX and EVEX form; PSUBW, PSUBD and PSUBQ take wider elements.

Forms

Every encoding of PSUBB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSUBB mm, m64` PSUBB_MMXq_MEMq	`NP 0F F8 /r`	MMX
`PSUBB mm, mm` PSUBB_MMXq_MMXq	`NP 0F F8 /r`	MMX
`PSUBB xmm, m128` PSUBB_XMMdq_MEMdq	`66 0F F8 /r`	SSE2
`PSUBB xmm, xmm` PSUBB_XMMdq_XMMdq	`66 0F F8 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: a7-b7, a6-b6, a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSUBB mm, mm/m64

for i in range(8):
    mm1.b[i] = mm1.b[i] - src2.b[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSUBB xmm, xmm/m128

for i in range(16):
    xmm1.b[i] = xmm1.b[i] - src2.b[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSUBB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSUBB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSUBB mm, mm/m64: mmx-mem
PSUBB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSUBB mm, mm/m64: may abort a TSX transaction
PSUBB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSUBB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_epi8` `__m128i _mm_sub_epi8(__m128i __a, __m128i __b)`	`PSUBB xmm, xmm` Legacy -msse2
`_mm_sub_pi8` `__m64 _mm_sub_pi8(__m64 __m1, __m64 __m2)`	`PSUBB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Bytes in compiled code#