PSUBD instruction (MMX, SSE2)

PSUBD subtracts doublewords element by element and keeps the low 32 bits of each difference, wrapping around the same way for signed and unsigned numbers: 4 in an XMM register, 2 in an MMX register. No flag records a borrow or an overflow. PSUBB covers what the family’s legacy forms share, from negation to the register minus itself. On Zen 5, the recorded psubd xmm8, [mem] turned 80000000h minus 7FFFFFFFh (the most negative doubleword minus the most positive) into 00000001h, and psubd xmm7, xmm11 turned 00000000h minus 00000001h into FFFFFFFFh, leaving bits 255:128 of the register as they were (see mixing SSE and AVX). There is no saturating form for doublewords: SSE’s saturating arithmetic covers only bytes and words.

Zeroing with it

Intel’s optimization manual lists PSUBD of an XMM register with itself among the dependency-breaking idioms that clear a register without loading a zero (Section 3.5.1.7), alongside the legacy PXOR, SUBPS/PD and the other wrapping PSUB forms; AMD’s Zen 5 guide instead lists only the VEX and EVEX forms, VPSUBD among them, as zeroing idioms (Section 2.9.2). In our builds at -O2, negating an int32_t array (-b[i]) compiles to a PXOR that zeros a register followed by a PSUBD of the value from it, in both GCC 14 and Clang 23.

int32_t and uint32_t differences at -O2 are one PSUBD per 4 doublewords with the second operand loaded by MOVDQU, in both compilers. A doubleword absolute value needs more: without SSSE3, b[i] < 0 ? -b[i] : b[i] builds a mask of the sign in every bit with PSRAD by 31, then computes (b ^ m) - m with PXOR and PSUBD, identically in GCC 14 and Clang 23. SSE2 has an arithmetic right shift for doublewords (PSRAD) but none for quadwords, which is why PSUBQ’s page shows the two compilers building that mask differently instead. With -march=x86-64-v2 both use PABSD instead.

AMD’s latency spreadsheet for Zen 5 gives PSUBD one cycle, four per cycle. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes; PSUBQ is the quadword form, whose MMX encoding came with SSE2 instead of MMX. VPSUBD is the VEX and EVEX form, the latter with masking and a broadcast doubleword.

Forms

Every encoding of PSUBD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSUBD mm, m64` PSUBD_MMXq_MEMq	`NP 0F FA /r`	MMX
`PSUBD mm, mm` PSUBD_MMXq_MMXq	`NP 0F FA /r`	MMX
`PSUBD xmm, m128` PSUBD_XMMdq_MEMdq	`66 0F FA /r`	SSE2
`PSUBD xmm, xmm` PSUBD_XMMdq_XMMdq	`66 0F FA /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSUBD mm, mm/m64

for i in range(2):
    mm1.d[i] = mm1.d[i] - src2.d[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSUBD xmm, xmm/m128

for i in range(4):
    xmm1.d[i] = xmm1.d[i] - src2.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSUBD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSUBD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSUBD mm, mm/m64: mmx-mem
PSUBD xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSUBD mm, mm/m64: may abort a TSX transaction
PSUBD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSUBD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_epi32` `__m128i _mm_sub_epi32(__m128i __a, __m128i __b)`	`PSUBD xmm, xmm` Legacy -msse2
`_mm_sub_pi32` `__m64 _mm_sub_pi32(__m64 __m1, __m64 __m2)`	`PSUBD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Zeroing with it#