PSUBQ instruction (SSE2)

PSUBQ subtracts quadwords and keeps the low 64 bits of each difference, the same for signed and unsigned numbers, as Intel’s optimization manual points out (Section 6.6.13): two in an XMM register, one in an MMX register. Unlike SUB, it sets no flags, so a borrow or an overflow goes unrecorded. On Zen 5, the recorded psubq xmm1, xmm2 turned 8000000000000000h minus FFFFFFFFFFFFFFFFh (-1) into 8000000000000001h and 7FFFFFFFFFFFFFFFh minus -1 into 8000000000000000h, and psubq mm7, [mem] turned 8000000000000000h minus 1 into 7FFFFFFFFFFFFFFFh. The XMM form kept bits 255:128 of its register (see mixing SSE and AVX). VPSUBQ is the VEX and EVEX form, and PSUBB covers what the subtractions share.

Quadwords in compiled code

int64_t and pointer differences compile to PSUBQ at -O2 in GCC 14 and Clang 23, and so does negation, from a zeroed register. A quadword absolute value is a case of its own: SSE2 has no arithmetic shift of quadwords and no PABSQ, so for b[i] < 0 ? -b[i] : b[i] both compilers build a mask m of the sign, all ones for negative elements, and compute (b ^ m) - m with PXOR and PSUBQ. In our builds for the baseline they make the mask differently:

GCC shifts the sign bit down with PSRLQ by 63 and subtracts the result from zero with a second PSUBQ.
Clang copies the upper doubleword of each quadword over the lower one with PSHUFD and shifts both right by 31 with PSRAD.

With -march=x86-64-v2, GCC compares with zero by PCMPGTQ for the mask, and Clang subtracts from zero and picks by the sign bit with BLENDVPD.

The MMX form came with SSE2, not with MMX, which had no quadword arithmetic. AMD’s latency spreadsheet for Zen 5 gives PSUBQ one cycle, four per cycle. A memory operand of the XMM form must be aligned to 16 bytes.

In the optimization guide

What the optimization guide says about PSUBQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Vectors and cryptography: pshufb, pmulld, paddq and psubq are slow on Silvermont and much faster from Goldmont on.

Forms

Every encoding of PSUBQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSUBQ mm, m64` PSUBQ_MMXq_MEMq	`NP 0F FB /r`	SSE2 + MMX
`PSUBQ mm, mm` PSUBQ_MMXq_MMXq	`NP 0F FB /r`	SSE2 + MMX
`PSUBQ xmm, m128` PSUBQ_XMMdq_MEMdq	`66 0F FB /r`	SSE2
`PSUBQ xmm, xmm` PSUBQ_XMMdq_XMMdq	`66 0F FB /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSUBQ mm, mm/m64

i = 0
mm1.q[i] = mm1.q[i] - src2.q[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSUBQ xmm, xmm/m128

for i in range(2):
    xmm1.q[i] = xmm1.q[i] - src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSUBQ mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSUBQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSUBQ mm, mm/m64: mmx-mem
PSUBQ xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSUBQ mm, mm/m64: may abort a TSX transaction
PSUBQ xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSUBQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_epi64` `__m128i _mm_sub_epi64(__m128i __a, __m128i __b)`	`PSUBQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2MMX` SSE2	SSE2 + MMX `CPUID.01H:EDX[26]` SSE2 `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Quadwords in compiled code#