PSUBSB instruction (MMX, SSE2)

PSUBSB subtracts bytes as signed numbers and clamps each difference to the range of a byte instead of letting it wrap: a difference above 127 becomes 7Fh and one below -128 becomes 80h, with nothing recorded. On Zen 5, the recorded psubsb xmm0, xmm13 turned FFh minus 01h into FEh (-1 minus 1), 80h minus 01h into 80h, where PSUBB gives 7Fh, and 00h minus 80h into 7Fh (0 minus -128), leaving bits 255:128 of the register as they were (see mixing SSE and AVX). PADDSB covers what the saturating byte family shares (the clamp, the intrinsics, the Zen 5 latency and throughput split from the plain wrapping forms); its partners here are PSUBSW for words and PSUBUSB for the unsigned subtraction.

In compiled code

In our builds at -O2 for the x86-64 baseline, over int8_t arrays:

The explicit clamp. int32_t s = b[i] - c[i]; a[i] = s > 127 ? 127 : s < -128 ? -128 : s; compiles to one PSUBSB per 16 bytes in Clang 23, the second operand loaded by MOVDQU. GCC 14 does not recognize it at all, even with -march=x86-64-v2: it widens each byte to a word and again to a doubleword, compares the doublewords against the bounds, and narrows the result back down with PACKUSDW and PACKUSWB, far more instructions than the one PSUBSB.
The intrinsic. _mm_subs_epi8 is PSUBSB in both compilers.

AMD’s latency spreadsheet for Zen 5 gives PSUBSB two cycles, two per cycle, on pipes FP0 and FP3, where PSUBB takes one cycle at four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSUBSB is the VEX and EVEX form.

Forms

Every encoding of PSUBSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSUBSB mm, m64` PSUBSB_MMXq_MEMq	`NP 0F E8 /r`	MMX
`PSUBSB mm, mm` PSUBSB_MMXq_MMXq	`NP 0F E8 /r`	MMX
`PSUBSB xmm, m128` PSUBSB_XMMdq_MEMdq	`66 0F E8 /r`	SSE2
`PSUBSB xmm, xmm` PSUBSB_XMMdq_XMMdq	`66 0F E8 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: a7-b7, a6-b6, a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSUBSB mm, mm/m64

for i in range(8):
    sa = mm1.sb[i]
    sb = src2.sb[i]
    mm1.b[i] = ssat(sa - sb, 8)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSUBSB xmm, xmm/m128

for i in range(16):
    sa = xmm1.sb[i]
    sb = src2.sb[i]
    xmm1.b[i] = ssat(sa - sb, 8)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSUBSB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSUBSB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSUBSB mm, mm/m64: mmx-mem
PSUBSB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSUBSB mm, mm/m64: may abort a TSX transaction
PSUBSB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSUBSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_subs_epi8` `__m128i _mm_subs_epi8(__m128i __a, __m128i __b)`	`PSUBSB xmm, xmm` Legacy -msse2
`_mm_subs_pi8` `__m64 _mm_subs_pi8(__m64 __m1, __m64 __m2)`	`PSUBSB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#