PSUBUSB instruction (MMX, SSE2)

PSUBUSB subtracts bytes as unsigned numbers and stops at zero: where the second operand’s byte is the larger, the result is 00h instead of a wrapped difference. On Zen 5, the recorded psubusb xmm0, [mem] turned 00h minus 01h, 01h minus FFh and 80h minus FFh into 00h and FFh minus 01h into FEh, and psubusb xmm4, xmm4 gave zero, leaving bits 255:128 alone in both (see mixing SSE and AVX). PSUBUSW is the word form, PADDUSB the addition, and PSUBB the subtraction that wraps.

A comparison as well

The result is zero exactly where the first byte is not greater than the second, so PSUBUSB followed by PCMPEQB against zero compares unsigned bytes, which SSE2 cannot do directly. In our builds at -O2 for the x86-64 baseline:

Clang 23 emits one PSUBUSB per 16 bytes for b[i] > c[i] ? b[i] - c[i] : 0, and for b[i] > 40 ? b[i] - 40 : 0 with a vector of 28h.
GCC 14 uses it as a test. It computes the first loop as PSUBB, then clears the bytes where PSUBUSB and PCMPEQB found b[i] not greater, with PANDN; it computes the second as PMAXUB with 28h and a PADDB of D8h, which is -40. For b[i] > c[i] ? -1 : 0 it takes PSUBUSB and two PCMPEQBs against zero, the second inverting the first, and for the range test (uint8_t)(b[i] - 'A') < 26 in a lowercase conversion, a PADDB of BFh, a PSUBUSB of 25 and PCMPEQB.

Intel’s optimization manual computes the absolute difference of two unsigned byte vectors with two PSUBUSBs, one in each direction, and a POR (Section 6.6.1): one of the two is always zero. Our compilers do not choose it for b[i] > c[i] ? b[i] - c[i] : c[i] - b[i]: Clang subtracts PMINUB from PMAXUB and GCC selects between the two differences. For sums of absolute differences, PSADBW does the whole job.

AMD’s latency spreadsheet for Zen 5 gives PSUBUSB two cycles and two per cycle, on pipes FP0 and FP3. Intel’s manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSUBUSB is the VEX and EVEX form.

Forms

Every encoding of PSUBUSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSUBUSB mm, m64` PSUBUSB_MMXq_MEMq	`NP 0F D8 /r`	MMX
`PSUBUSB mm, mm` PSUBUSB_MMXq_MMXq	`NP 0F D8 /r`	MMX
`PSUBUSB xmm, m128` PSUBUSB_XMMdq_MEMdq	`66 0F D8 /r`	SSE2
`PSUBUSB xmm, xmm` PSUBUSB_XMMdq_XMMdq	`66 0F D8 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: a7-b7, a6-b6, a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSUBUSB mm, mm/m64

for i in range(8):
    mm1.b[i] = usat(mm1.b[i] - src2.b[i], 8)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSUBUSB xmm, xmm/m128

for i in range(16):
    a = xmm1.b[i]
    b = src2.b[i]
    xmm1.b[i] = usat(a - b, 8)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSUBUSB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSUBUSB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSUBUSB mm, mm/m64: mmx-mem
PSUBUSB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSUBUSB mm, mm/m64: may abort a TSX transaction
PSUBUSB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSUBUSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_subs_epu8` `__m128i _mm_subs_epu8(__m128i __a, __m128i __b)`	`PSUBUSB xmm, xmm` Legacy -msse2
`_mm_subs_pu8` `__m64 _mm_subs_pu8(__m64 __m1, __m64 __m2)`	`PSUBUSB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

A comparison as well#