PSUBUSW instruction (MMX, SSE2)

PSUBUSW subtracts words as unsigned numbers and stops at zero: where the second operand’s word is the larger, the result is 0000h instead of a wrapped difference. On Zen 5, the recorded psubusw xmm0, xmm13 turned FFFFh (65535) minus 0001h into FFFEh and 0001h minus FFFFh into 0000h, leaving bits 255:128 of the register as they were (see mixing SSE and AVX). PSUBUSB covers what the saturating family shares, including the comparison trick that PSUBUSB plus PCMPEQB gives for unsigned bytes; its partners here are PADDUSW for the addition and PSUBSW for the signed subtraction.

Unsigned order in compiled code

PSUBUSW followed by PCMPEQW against zero compares unsigned words the way PSUBUSB and PCMPEQB compare unsigned bytes. In our builds at -O2 over uint16_t arrays:

Clamped differences. b[i] > c[i] ? b[i] - c[i] : 0 is one PSUBUSW per 8 words in both compilers.
The comparison. b[i] > c[i] ? 0xffff : 0 takes PSUBUSW and two PCMPEQWs against zero in GCC 14, the second inverting the first, the same idiom PCMPEQW’s page describes for the unsigned order of words. Clang 23 instead flips the sign bit of both operands with PXOR against 8000h and compares the results as signed numbers with PCMPGTW, never emitting PSUBUSW for this form at all.

AMD’s latency spreadsheet for Zen 5 gives PSUBUSW two cycles, two per cycle, on pipes FP0 and FP3, where PSUBW takes one cycle at four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSUBUSW is the VEX and EVEX form.

Forms

Every encoding of PSUBUSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSUBUSW mm, m64` PSUBUSW_MMXq_MEMq	`NP 0F D9 /r`	MMX
`PSUBUSW mm, mm` PSUBUSW_MMXq_MMXq	`NP 0F D9 /r`	MMX
`PSUBUSW xmm, m128` PSUBUSW_XMMdq_MEMdq	`66 0F D9 /r`	SSE2
`PSUBUSW xmm, xmm` PSUBUSW_XMMdq_XMMdq	`66 0F D9 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: a7-b7, a6-b6, a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSUBUSW mm, mm/m64

for i in range(4):
    a = mm1.w[i]
    b = src2.w[i]
    mm1.w[i] = usat(a - b, 16)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSUBUSW xmm, xmm/m128

for i in range(8):
    a = xmm1.w[i]
    b = src2.w[i]
    xmm1.w[i] = usat(a - b, 16)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSUBUSW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSUBUSW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSUBUSW mm, mm/m64: mmx-mem
PSUBUSW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSUBUSW mm, mm/m64: may abort a TSX transaction
PSUBUSW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSUBUSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_subs_epu16` `__m128i _mm_subs_epu16(__m128i __a, __m128i __b)`	`PSUBUSW xmm, xmm` Legacy -msse2
`_mm_subs_pu16` `__m64 _mm_subs_pu16(__m64 __m1, __m64 __m2)`	`PSUBUSW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Unsigned order in compiled code#