PSUBW instruction (MMX, SSE2)

PSUBW subtracts words element by element, 8 in an XMM register or 4 in an MMX register, and keeps the low 16 bits of each difference, wrapping around with no flags. On Zen 5, the recorded psubw xmm1, xmm2 turned 7FFFh minus FFFFh into 8000h (32767 plus 1 wrapping to -32768) and 0000h minus 8000h into 8000h: the most negative word is its own negation. Bits 255:128 of the register kept their value (see mixing SSE and AVX). PSUBB covers what the subtractions share, from negation to the register minus itself; PSUBSW and PSUBUSW clamp instead of wrapping.

Words in compiled code

In our builds at -O2 for the x86-64 baseline:

int16_t arrays. a[i] = b[i] - c[i] is one PSUBW per 8 words with the second operand from memory, in GCC 14 and Clang 23.
Differences of bytes. Two uint8_t arrays subtracted into int16_t give -255 to 255, which a word holds. GCC loads 16 bytes of each and zero-extends them with PUNPCKLBW and PUNPCKHBW against a zeroed register, Clang loads 8 with MOVQ and uses PUNPCKLBW alone; then each subtracts with PSUBW. With -march=x86-64-v2 both widen with PMOVZXBW.
Absolute values. Without SSSE3, b[i] < 0 ? -b[i] : b[i] is PSUBW from zero and PMAXSW of the value and its negation in both compilers, the sequence Intel’s optimization manual gives for words (Section 6.6.3). 8000h stays 8000h, as above. With -march=x86-64-v2 both use PABSW, and the absolute difference of two int16_t arrays becomes PSUBW followed by PABSW, which is the manual’s example for signed numbers (Section 6.6.2).

AMD’s latency spreadsheet for Zen 5 gives PSUBW one cycle, four per cycle. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPSUBW is the VEX and EVEX form.

Forms

Every encoding of PSUBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PSUBW mm, m64` PSUBW_MMXq_MEMq	`NP 0F F9 /r`	MMX
`PSUBW mm, mm` PSUBW_MMXq_MMXq	`NP 0F F9 /r`	MMX
`PSUBW xmm, m128` PSUBW_XMMdq_MEMdq	`66 0F F9 /r`	SSE2
`PSUBW xmm, xmm` PSUBW_XMMdq_XMMdq	`66 0F F9 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: a7-b7, a6-b6, a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PSUBW mm, mm/m64

for i in range(4):
    mm1.w[i] = mm1.w[i] - src2.w[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PSUBW xmm, xmm/m128

for i in range(8):
    xmm1.w[i] = xmm1.w[i] - src2.w[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PSUBW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PSUBW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PSUBW mm, mm/m64: mmx-mem
PSUBW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PSUBW mm, mm/m64: may abort a TSX transaction
PSUBW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PSUBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sub_epi16` `__m128i _mm_sub_epi16(__m128i __a, __m128i __b)`	`PSUBW xmm, xmm` Legacy -msse2
`_mm_sub_pi16` `__m64 _mm_sub_pi16(__m64 __m1, __m64 __m2)`	`PSUBW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Words in compiled code#