PTEST instruction (SSE4.1)

PTEST is a 128-bit TEST that writes no register and answers two questions at once in the flags. ZF says whether the operands share no set bit (their AND is zero); CF says whether every bit set in the source is also set in the destination (the source ANDed with the inverted destination is zero). OF, SF, AF and PF are cleared. Intel’s optimization manual presents it for branching on vector conditions: one PTEST and a jump leave a vectorized loop early when any element needs scalar handling (Section 6.6.15).

Reading the answer

Each intrinsic stands for one condition after PTEST:

Intrinsic	True when	Instruction after PTEST
`_mm_testz_si128(a, b)`	`a & b` is all zeros	SETE or JE (ZF)
`_mm_testc_si128(a, b)`	`~a & b` is all zeros	SETB or JB (CF)
`_mm_testnzc_si128(a, b)`	neither	SETA or JA

PTEST of a register with itself is the all-zero check, and an XOR in front of it makes a 16-byte equality test. GCC 14 and Clang 23 at -O2 with -msse4.1 compile memcmp(p, q, 16) == 0 to two MOVDQUs, PXOR, PTEST and SETE. For the SSE2 baseline Clang uses PCMPEQB, PMOVMSKB and a compare with FFFFh, and GCC two 64-bit XORs in general-purpose registers. Given that PCMPEQB and PMOVMSKB sequence written with intrinsics, Clang turns it into PXOR and PTEST once SSE4.1 is allowed; GCC keeps it.

Its relatives

VPTEST adds a 256-bit form, and VTESTPS and VTESTPD look only at the sign bit of each element: with -mavx, Clang compiles _mm_movemask_ps(v) != 0 to VTESTPS of v with itself, where GCC keeps MOVMSKPS and TEST. In Crestmont the 256-bit forms take two dependent micro-ops (Intel’s optimization manual, Section 4.1.9.5). AVX-512 has no flag-setting test for its wider registers: VPTESTMD and its kin write a mask register, which KORTESTW turns into flags.

The legacy form with a memory operand needs it aligned to 16 bytes.

Forms

Every encoding of PTEST that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PTEST xmm, m128` PTEST_XMMdq_MEMdq	`66 0F 38 17 /r`	SSE4.1
`PTEST xmm, xmm` PTEST_XMMdq_XMMdq	`66 0F 38 17 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A test of all the bits: ZF is set if xmm1 AND xmm2 is zero, CF if NOT xmm1 AND xmm2 is.

ZF and CF each depend on every element of xmm1 and xmm2. RFLAGS: CF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

zf = xmm1.read() & src2.read() == 0
cf = ~xmm1.read() & src2.read() == 0
of = sf = af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PTEST xmm, xmm/m128`
`xmm`	explicit	read
`xmm/m128`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PTEST, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_test_all_zeros` `int _mm_test_all_zeros(__m128i M, __m128i V)`	`PTEST xmm, xmm` Legacy -msse4.1
`_mm_test_mix_ones_zeros` `int _mm_test_mix_ones_zeros(__m128i M, __m128i V)`	`PTEST xmm, xmm` Legacy -msse4.1
`_mm_testc_si128` `int _mm_testc_si128(__m128i __M, __m128i __V)`	`PTEST xmm, xmm` Legacy -msse4.1
`_mm_testnzc_si128` `int _mm_testnzc_si128(__m128i __M, __m128i __V)`	`PTEST xmm, xmm` Legacy -msse4.1
`_mm_testz_si128` `int _mm_testz_si128(__m128i __M, __m128i __V)`	`PTEST xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Reading the answer#

Its relatives#