PUNPCKHBW instruction (MMX, SSE2)

PUNPCKHBW interleaves the high bytes of its two operands, a byte of the destination, a byte of the source, and so on: 8 results in an XMM register, 4 in an MMX register. It is the legacy SSE and MMX form of VPUNPCKHBW, whose page covers the interleave itself and how the VEX and EVEX forms keep each 128-bit lane separate. On Zen 5, the recorded punpckhbw mm0, mm4 combined bytes 4 to 7 of MM0, 8Eh, 9Bh, A8h and B5h, with those of MM4, AAh, B7h, C4h and D1h, into 8Eh, AAh, 9Bh, B7h, A8h, C4h, B5h and D1h.

What the legacy form adds

The destination doubles as the first source. The MMX memory operand is a full 64-bit mm/m64, all eight bytes, even though only the high four feed the result; the XMM memory operand is 128 bits and must be aligned to 16 bytes, for the same reason. The 128-bit legacy form leaves bits 255:128 of the register as they were, unlike the VEX form, which zeros them (see mixing SSE and AVX). In our builds at -O2, a straight call to the intrinsic compiles to the single instruction in GCC 14 and Clang 23 regardless of -march, since both the MMX and the 128-bit SSE2 forms need no newer feature than the baseline.

AMD’s latency spreadsheet for Zen 5 gives PUNPCKHBW a latency of one cycle, four per cycle, for the XMM form with a register source; the MMX form with a memory source instead runs at two per cycle.

Forms

Every encoding of PUNPCKHBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKHBW mm, m64` PUNPCKHBW_MMXq_MEMq	`NP 0F 68 /r`	MMX
`PUNPCKHBW mm, mm` PUNPCKHBW_MMXq_MMXd	`NP 0F 68 /r`	MMX
`PUNPCKHBW xmm, m128` PUNPCKHBW_XMMdq_MEMdq	`66 0F 68 /r`	SSE2
`PUNPCKHBW xmm, xmm` PUNPCKHBW_XMMdq_XMMq	`66 0F 68 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high bytes of both sources alternate in the result, those of xmm1 in the even places.

Result bytes 15 to 0: b15, a15, b14, a14, b13, a13, b12, a12, b11, a11, b10, a10, b9, a9, b8, a8.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PUNPCKHBW mm, mm/m64

src1 = mm1.read()  # mm1 as it was
for i in range(8):
    j = i // 2 + 4
    if i % 2 == 0:
        mm1.b[i] = src1.b[j]
    else:
        mm1.b[i] = src2.b[j]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PUNPCKHBW xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(16):
    j = i // 2 + 8
    if i % 2 == 0:
        xmm1.b[i] = src1.b[j]
    else:
        xmm1.b[i] = src2.b[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKHBW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PUNPCKHBW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PUNPCKHBW mm, mm/m64: mmx-mem
PUNPCKHBW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PUNPCKHBW mm, mm/m64: may abort a TSX transaction
PUNPCKHBW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKHBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpackhi_epi8` `__m128i _mm_unpackhi_epi8(__m128i __a, __m128i __b)`	`PUNPCKHBW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

What the legacy form adds#