PUNPCKHDQ instruction (MMX, SSE2)

PUNPCKHDQ interleaves the high doublewords of its two operands: doubleword 2 of the destination, doubleword 2 of the source, then doubleword 3 of each (in the MMX form, doubleword 1 of each). With the same register twice it doubles each high element: on Zen 5, punpckhdq xmm4, xmm4 turned the doublewords 05F8EBDEh and 392C1F12h into 05F8EBDEh, 05F8EBDEh, 392C1F12h, 392C1F12h and kept bits 511:128 of ZMM4, and punpckhdq mm3, mm3 copied the high half of MM3 into both halves. PUNPCKLDQ takes the low halves and covers what compilers build with the pair; PUNPCKLBW describes the whole family.

The upper half of a vector

Moving an element down. For v[2] of a vector of four ints, GCC 14 at -O2 for the SSE2 baseline emits punpckhdq xmm0, xmm0 and MOVD; Clang 23 uses PSHUFD with EEh. With -march=x86-64-v2, GCC extracts with PEXTRD and Clang with its floating-point twin, EXTRACTPS.
Widening it. GCC’s baseline loops widen the upper two doublewords of a 16-byte load with PUNPCKHDQ, against a zeroed register for uint64_t results and against the sign masks of PCMPGTD for int64_t ones, where SSE4.1 code shifts the half down with PSRLDQ and uses PMOVZXDQ or PMOVSXDQ.
Regrouping pairs. Intel’s optimization manual shows the pair unpacking two vectors of words without interleaving them: PUNPCKLDQ puts the two low words of each operand side by side, PUNPCKHDQ the two high ones (Section 6.4.5). The 4x4 transpose of doublewords uses the same step before PUNPCKLQDQ and PUNPCKHQDQ.

The SSE2 form needs a memory operand aligned to 16 bytes, of which the upper eight count. AMD’s latency spreadsheet for Zen 5 gives PUNPCKHDQ one macro-op with a latency of one cycle, four per cycle. VPUNPCKHDQ is the VEX and EVEX form, which interleaves within each 128-bit lane.

Forms

Every encoding of PUNPCKHDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKHDQ mm, m64` PUNPCKHDQ_MMXq_MEMq	`NP 0F 6A /r`	MMX
`PUNPCKHDQ mm, mm` PUNPCKHDQ_MMXq_MMXd	`NP 0F 6A /r`	MMX
`PUNPCKHDQ xmm, m128` PUNPCKHDQ_XMMdq_MEMdq	`66 0F 6A /r`	SSE2
`PUNPCKHDQ xmm, xmm` PUNPCKHDQ_XMMdq_XMMq	`66 0F 6A /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high doublewords of both sources alternate in the result, those of xmm1 in the even places.

Result doublewords 3 to 0: b3, a3, b2, a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PUNPCKHDQ mm, mm/m64

src1 = mm1.read()  # mm1 as it was
for i in range(2):
    j = i // 2 + 1
    if i % 2 == 0:
        mm1.d[i] = src1.d[j]
    else:
        mm1.d[i] = src2.d[j]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PUNPCKHDQ xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = i // 2 + 2
    if i % 2 == 0:
        xmm1.d[i] = src1.d[j]
    else:
        xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKHDQ mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PUNPCKHDQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PUNPCKHDQ mm, mm/m64: mmx-mem
PUNPCKHDQ xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PUNPCKHDQ mm, mm/m64: may abort a TSX transaction
PUNPCKHDQ xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKHDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpackhi_epi32` `__m128i _mm_unpackhi_epi32(__m128i __a, __m128i __b)`	`PUNPCKHDQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

The upper half of a vector#